SMD5962-92324 Просмотр технического описания (PDF) - Simtek Corporation
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SMD5962-92324 Datasheet PDF : 16 Pages
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STK11C68 (SMD5962–92324)
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
STK11C68-25
MIN MAX
12
tAVAV
13 tWLWH
14 tELWH
15 tDVWH
16 tWHDX
17 tAVWH
18 tAVWL
19 tWHAX
20 tWLQZh, i
21 tWHQX
tAVAV
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
tWC Write Cycle Time
25
tWP Write Pulse Width
20
tCW Chip Enable to End of Write
20
tDW Data Set-up to End of Write
10
tDH Data Hold after End of Write
0
tAW Address Set-up to End of Write
20
tAS Address Set-up to Start of Write
0
tWR Address Hold after End of Write
0
tWZ Write Enable to Output Disable
10
tOW Output Active after End of Write
5
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledj
ADDRESS
12
tAVAV
14
tELWH
E
(VCC = 5.0V + 10%)
STK11C68-35 STK11C68-45 STK11C68-55
UNITS
MIN MAX MIN MAX MIN MAX
35
45
55
ns
25
30
45
ns
25
30
45
ns
12
15
30
ns
0
0
0
ns
25
30
45
ns
0
0
0
ns
0
0
0
ns
13
15
35
ns
5
5
5
ns
19
tWHAX
18
tAVWL
W
17
tAVWH
13
tWLWH
DATA IN
DATA OUT
20
tWLQZ
PREVIOUS DATA
15
tDVWH
DATA VALID
HIGH IMPEDANCE
SRAM WRITE CYCLE #2: E Controlledj
ADDRESS
E
18
tAVEL
12
tAVAV
14
tELEH
16
tWHDX
21
tWHQX
19
tEHAX
W
DATA IN
DATA OUT
17
tAVEH
13
tWLEH
15
tDVEH
DATA VALID
HIGH IMPEDANCE
16
tEHDX
Document Control #ML0007 Rev 0.3
5
February, 2007
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