RS5C316A Просмотр технического описания (PDF) - RICOH Co.,Ltd.
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RS5C316A Datasheet PDF : 38 Pages
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RS5C316A/B
2.1-2 (BSY)
When the BSY bit is 1, the clock and calendar counter are being updated. Consequently, write operation should
be performed for the counters when the BSY bit is 0. Meanwhile, read operation is normally performed for the
counters when the BSY bit is 0, but can be performed without checking the BSY bit as long as appropriate software
is provided for preventing read errors. (Refer to 13. Typical Software-based Operations.) The BSY bit is set to 1 in
the following three cases:
(I) Adjustment of second digits
by ±30 second
(II) Second digits increment by 1
(Subject to 1-sec digit carry when
the WTEN bit is switched from 0 to 1)
(III) Ordinary 1-sec digit carry
MAX.122.1 µs
Setting of the
ADJ bit to 1
Completion of second
digit adjustment
MAX.91.6 µs
Setting of the End of second digit
WTEN bit to 1 increment by 1
91.6 µs
End of second digit carry pulse
2.1-3 (WTEN)
The WTEN bit should be set to 0 to check that the BSY bit is 0 when performing read and write operations for
the clock and calendar counters. For read operation, the WTEN bit may be left as 1 without checking the BSY bit as
long as appropriate measures such as read repetition are provided for preventing read errors. The WTEN bit
should be set to 1 after completing read and write operations, or will automatically be set to 1 by switching the CE
pin to the low level. If 1-second digit carry occurs when the WTEN bit is 0, a second digit increment by 1 occurs
when the WTEN bit is set to 1. There may be a possibility causing a time delay when it takes 1/1024 second or
more to set WTEN bit from 0 to 1, Read data in state of WTEN=1 in such a case. (Refer to the item 13.3)
2.1-4 (XSTP)
The XSTP bit senses the oscillator halt. When the CE pin is held at the low level, the XSTP bit is set to 1 once
the crystal oscillator is stopped after initial power-on or supply voltage drop and left to be 1 after it is restarted.
When the CE pin is held at the high level, the XSTP bit is left as it was when the CE pin was held at the low level
without checking oscillation stop. As such, the XSTP bit can be used to validate clock and calendar count data after
power-on or supply voltage drop. The XSTP bit is set to 0 when any data is written to the control register 1 (at Eh)
with ordinary oscillation.
2.1-5 (ALFG)
The ALFG bit can be set to 1 when the ALE bit set to 1 with alarm interruption (INTR=L).
ALFG
INTR
Matched alarm Matched alarm ALFG is written to 0 Matched alarm
register
register
register
9
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