RF2958 Просмотр технического описания (PDF) - RF Micro Devices
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RF2958 Datasheet PDF : 20 Pages
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RF2958
Parameter
Digital Input
Specifications
Apply to pins: SSB, SDI, SCLK,
MODE0, MODE1
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input High Static Current (IIH)
Input Low Static Current (IIL)
Reset Time
Apply to pins: SSB, SDI, SCLK
Input Setup Time (TSU)*
Input Hold Time (THLD)*
Input Rise/Fall Time (TRFI)
Input Clock to Select Time (TCS)
Input Clock Pulse Width High
(TCWH)
Input Clock Pulse Width Low
(TCWL)
PLL Recalibration Pulse Width
(TRC)
Digital Driver Output
Apply to pin: SDI (output mode)
Output High Voltage (VOH)
Output Low Voltage (VOL)
Output Rise/Fall Time (TRFO)
Output Current Source (|IOH|)
Output Current Sink (|IOL|)
Specification
Min.
Typ.
Max.
0.7 VDD
0.3 VDD
5
5
50
5
5
5
5
22
22
1/fr
0.8 VDD
3.8
10
0.2 VDD
5
Unit
V
V
µA
µA
µs
ns
ns
ns
ns
ns
ns
s
V
V
ns
mA
mA
MCLK Input (AC-Coupled)
Apply to pin: MCLK
Peak-to-Peak Input Voltage
500
mV
(VP-P)
DC Bias at MCLK (MCLK_DC)
0.6
1.1
V
Specification Valid Range
Temperature
-30
+70
°C
Supply Voltage
2.7
3.0
3.6
V
Transmit Current
50
68
80
mA
Receive Current
30
52
60
mA
Idle Current
5
28
40
mA
Reset Current
1
2
mA
Hibernate Current
0.2
0.5
mA
*Setup and Hold Times are measured from the time where the waveforms cross VDD/2.
Condition
Exiting Reset mode or using SPI Reset
For fr=22MHz, TRC is 45.5ns minimum
With 1mA load
With 1mA load
With 20pF maximum load capacitance mea-
sured from 10% to 90% of output voltage
Output at (VDD-0.3V)
Output at 0.3V
MCLK can be driven DC-coupled by a
CMOS clock oscillator with rail-to-rail out-
puts. Other oscillator configurations may
require AC-coupling.
MODE0=0, MODE1=1
MODE0=1, MODE1=0
MODE0=0, MODE1=0
MODE0=1, MODE1=1
11-266
Rev A0 050209
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