MTV012E Просмотр технического описания (PDF) - Myson Century Inc
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MTV012E Datasheet PDF : 14 Pages
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MYSON
TECHNOLOGY
MTV012E
timer function is disabled after power-on reset; the user can activate this function by setting WEN, and
clear the timer by setting WCLR.
reg name
MSTUS
MBUF
INTFLG
MCTR
INTEN
FIFO
WDT
SLVCTR
SLVSTUS
SLVINT
SLVBUF
SLVADR
addr
00h (r)
10h (r/w)
50h (r/w)
00h (w)
60h (w)
70h (w)
80h (w)
90h (w)
91h (r)
91h (w)
92h (r)
93h (w)
bit7
X
MBUF7
HPRchg
LS1
EHPR
FIFO7
WEN
ENSLV
WADR
X
SLVbuf7
SLVadr7
bit6
SCLERR
MBUF6
VPRchg
LS0
EVPR
FIFO6
WCLR
SLVsel
SLVS
X
SLVbuf6
SLVadr6
bit5
DDC2
MBUF5
HPLchg
LDFIFO
EHPL
FIFO5
CLRDDC
ESLVBI
SLVBI
X
SLVbuf5
SLVadr5
bit4
BERR
MBUF4
VPLchg
M256
EVPL
FIFO4
DIV253
ESLVMI
SLVMI
SLVMI
SLVbuf4
SLVadr4
bit3
HFREQ
MBUF3
HFchg
M128
EHF
FIFO3
LVSEL
X
X
X
SLVbuf3
SLVadr3
bit2
FIFOH
MBUF2
VFchg
ACK
EVF
FIFO2
WDT2
X
X
X
SLVbuf2
SLVadr2
bit1
FIFOL
MBUF1
FIFOI
P
EFIFO
FIFO1
WDT1
X
X
X
SLVbuf1
SLVadr1
bit0
BUSY
MBUF0
MI
S
EMI
FIFO0
WDT0
X
X
X
SLVbuf0
X
MCTR (w) : Master IIC interface control register.
LS1, LS0
= 11 → FIFOL is the status which has a FIFO depth of < 5.
= 10 → FIFOL is the status which has a FIFO depth of < 4.
= 01 → FIFOL is the status which has a FIFO depth of < 3.
= 00 → FIFOL is the status which has a FIFO depth of < 2.
LDFIFO
= 1 → FIFO will be written while S/W reads MBUF.
M256
= 1 → Disables host writing EEPROM when address is over 256.
M128
= 1 → Disables host writing EEPROM when address is over 128.
ACK
= 1 → In receiving mode, there is no acknowledgment by MTV012E.
= 0 → In receiving mode, ACK is returned by MTV012E.
S, P
= ↑,0 → Start condition when Master IIC is not transferring.
= X,↑ → Stop condition when Master IIC is not transferring.
= 1,X → Will resume transfer after a read/write MBUF operation.
= X,0 → Forces HSCL low and occupies the IIC bus.
* MTV012E uses a 100KHz clock to sample the S/P bit; any pulse should sustain at least 20us.
* A write/read MBUF operation can be recognized only after 10us of the MI flag's rising edge.
MSTUS (r) : Master IIC interface status register.
SCLERR
= 1 → The ISCL pin is pulled-low by other devices during the
transfer, and cleared when S=0.
DDC2
= 1 → DDC2B is active.
= 0 → MTV012E remains in DDC1 mode.
BERR
= 1 → IIC bus error, no ACK received from the slave, updated every time
when slave sends ACK on the ISDA pin.
HFREQ
= 1 → MTV012E detects a higher than 200Hz clock on the VSYNC pin.
FIFOH
= 1 → FIFO high indicated.
FIFOL
= 1 → FIFO low indicated.
BUSY
= 1 → Host drives the HSCL pin to low.
* While writing FIFO, the FIFOH/FIFOL flag will reflect the FIFO condition after 30us.
INTFLG (w) :
FIFOI
MI
Interrupt flag. An interrupt event will set its individual flag and, if the corresponding
interrupt enable bit is set, the 8051 INT1 source will be driven by a zero level. Software
MUST clear this register while serving the interrupt routine.
= 1 → No action.
= 0 → Clears FIFOI flag.
= 1 → No action.
= 0 → Clears Master IIC bus interrupt flag (MI).
11/14
MTV012E Revision 1.2 12/23/1998
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