R8C2G Просмотр технического описания (PDF) - Renesas Electronics

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R8C2G

RENESAS MCU R8C FAMILY / R8C/2x SERIES

Renesas Electronics 

Table of Contents

SFR Page Reference ........................................................................................................................... B - 1

1. Overview ......................................................................................................................................... 1

1.1 Features ..................................................................................................................................................... 1

1.1.1 Applications .......................................................................................................................................... 1

1.1.2 Specifications ........................................................................................................................................ 1

1.2 Product List ............................................................................................................................................... 3

1.3 Block Diagram .......................................................................................................................................... 4

1.4 Pin Assignment .......................................................................................................................................... 5

1.5 Pin Functions ............................................................................................................................................. 7

2. Central Processing Unit (CPU) ....................................................................................................... 8

2.1 Data Registers (R0, R1, R2, and R3) ........................................................................................................ 9

2.2 Address Registers (A0 and A1) ................................................................................................................. 9

2.3 Frame Base Register (FB) ......................................................................................................................... 9

2.4 Interrupt Table Register (INTB) ................................................................................................................ 9

2.5 Program Counter (PC) ............................................................................................................................... 9

2.6

2.7

2.8

2.8.1

2.8.2

2.8.3

User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .................................................................... 9

Static Base Register (SB) .......................................................................................................................... 9

Flag Register (FLG) .................................................................................................................................. 9

Carry Flag (C) ....................................................................................................................................... 9

Debug Flag (D) ..................................................................................................................................... 9

Zero Flag (Z) ......................................................................................................................................... 9

2.8.4 Sign Flag (S) ......................................................................................................................................... 9

2.8.5 Register Bank Select Flag (B) .............................................................................................................. 9

2.8.6 Overflow Flag (O) ................................................................................................................................ 9

2.8.7

2.8.8

2.8.9

2.8.10

Interrupt Enable Flag (I) ..................................................................................................................... 10

Stack Pointer Select Flag (U) .............................................................................................................. 10

Processor Interrupt Priority Level (IPL) ............................................................................................. 10

Reserved Bit ........................................................................................................................................ 10

3. Memory .......................................................................................................................................... 11

4. Special Function Registers (SFRs) ............................................................................................... 12

5. Resets ........................................................................................................................................... 24

5.1 Hardware Reset ....................................................................................................................................... 27

5.1.1 When Power Supply is Stable ............................................................................................................. 27

5.1.2 Power On ............................................................................................................................................ 27

5.2 Power-On Reset Function ....................................................................................................................... 29

5.3 Voltage Monitor 0 Reset ......................................................................................................................... 30

5.4 Voltage Monitor 1 Reset ......................................................................................................................... 30

5.5 Voltage Monitor 2 Reset ......................................................................................................................... 30

5.6 Watchdog Timer Reset ............................................................................................................................ 31

5.7 Software Reset ......................................................................................................................................... 31

6. Voltage Detection Circuit .............................................................................................................. 32

6.1 VCC Input Voltage .................................................................................................................................. 40

6.1.1 Monitoring Vdet0 ............................................................................................................................... 40

A-1

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