R5F212C7SDFP Просмотр технического описания (PDF) - Renesas Electronics

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R5F212C7SDFP

RENESAS MCU

Renesas Electronics 

R8C/2C Group, R8C/2D Group

1.3 Block Diagram

Figure 1.3 shows a Block Diagram.

1. Overview

8

8

8

8

32

8

I/O ports

Port P0

Port P1

Port P2

Port P3

Port P4

Port P5

Peripheral functions

Timers

Timer RA (8 bits × 1)

Timer RB (8 bits × 1)

Timer RC (16 bits × 1)

Timer RD (16 bits × 2)

Timer RE (8 bits × 1)

Timer RF (16 bits × 1)

UART or

clock synchronous serial I/O

(8 bits × 3)

I2C bus or SSU

(8 bits × 1)

LIN module

System clock generation

circuit

XIN-XOUT

High-speed on-chip oscillator

Low-speed on-chip oscillator

XCIN-XCOUT

Watchdog timer

(15 bits)

A/D converter

(10 bits × 20 channels)

D/A converter

(8 bits × 2)

R8C/Tiny Series CPU core

R0H R0L

R1H R1L

R2

R3

A0

A1

FB

SB

USP

ISP

INTB

PC

FLG

Memory

ROM(1)

RAM(2)

Multiplier

Figure 1.3 Block Diagram

NOTES:

1. ROM size varies with MCU type.

2. RAM size varies with MCU type.

Rev.1.00 Feb 09, 2007 Page 8 of 55

REJ03B0183-0100

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