R5F21206JFP Просмотр технического описания (PDF) - Renesas Electronics

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R5F21206JFP

RENESAS MCU

Renesas Electronics 

R8C/20 Group, R8C/21 Group

1.3 Block Diagram

Figure 1.1 shows a Block Diagram.

1. Overview

I/O port

8

8

8

6

33

8

Port P0

Port P1

Port P2

Port P3

Port P4

Port P6

Timer

Timer RA (8 bits)

Timer RB (8 bits)

Timer RD (16 bits × 2 channels)

Timer RE (8 bits)

Watchdog timer

(15 bits)

Figure 1.1 Block Diagram

A/D converter

(10 bits × 12 channels)

UART or

clock synchronous serial I/O

(8 bits × 1 channel)

UART

(8 bits × 1 channel)

I2C bus interface or

clock synchronous serial I/O

with chip select

(8 bits × 1 channel)

LIN module

(1 channel)

System clock

generation circuit

XIN-XOUT

High-speed on-chip oscillator

Low-speed on-chip oscillator

R8C CPU core

R0H R0L

R1H R1L

R2

R3

A0

A1

FB

SB

USP

ISP

INTB

PC

FLG

Memory

ROM(1)

RAM(2)

Multiplier

NOTES:

1. ROM size depends on MCU type.

2. RAM size depends on MCU type.

Rev.2.00 Aug 27, 2008 Page 4 of 458

REJ09B0250-0200

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