R5E70835RN80FTV Просмотр технического описания (PDF) - Renesas Electronics

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R5E70835RN80FTV

32-Bit RISC Microcomputer SuperH™ RISC engine Family

Renesas Electronics 

Section 7 User Break Controller (UBC)............................................................ 135

7.1 Features.............................................................................................................................. 135

7.2 Input/Output Pins............................................................................................................... 137

7.3 Register Descriptions ......................................................................................................... 138

7.3.1 Break Address Register A (BARA) ...................................................................... 139

7.3.2 Break Address Mask Register A (BAMRA)......................................................... 139

7.3.3 Break Bus Cycle Register A (BBRA)................................................................... 140

7.3.4 Break Data Register A (BDRA) (Only in F-ZTAT Version)................................ 142

7.3.5 Break Data Mask Register A (BDMRA) (Only in F-ZTAT Version) .................. 143

7.3.6 Break Address Register B (BARB) ...................................................................... 144

7.3.7 Break Address Mask Register B (BAMRB) ......................................................... 145

7.3.8 Break Data Register B (BDRB) (Only in F-ZTAT Version) ................................ 146

7.3.9 Break Data Mask Register B (BDMRB) (Only in F-ZTAT Version)................... 147

7.3.10 Break Bus Cycle Register B (BBRB) ................................................................... 148

7.3.11 Break Control Register (BRCR) ........................................................................... 150

7.3.12 Execution Times Break Register (BETR) (Only in F-ZTAT Version)................. 155

7.3.13 Branch Source Register (BRSR) (Only in F-ZTAT Version)............................... 156

7.3.14 Branch Destination Register (BRDR) (Only in F-ZTAT Version)....................... 157

7.4 Operation ........................................................................................................................... 158

7.4.1 Flow of the User Break Operation ........................................................................ 158

7.4.2 User Break on Instruction Fetch Cycle ................................................................. 159

7.4.3 User Break on Data Access Cycle ........................................................................ 160

7.4.4 Sequential Break ................................................................................................... 161

7.4.5 Value of Saved Program Counter ......................................................................... 161

7.4.6 PC Trace ............................................................................................................... 162

7.4.7 Usage Examples.................................................................................................... 163

7.5 Usage Notes ....................................................................................................................... 168

Section 8 Data Transfer Controller (DTC)........................................................171

8.1 Features.............................................................................................................................. 171

8.2 Register Descriptions ......................................................................................................... 173

8.2.1 DTC Mode Register A (MRA) ............................................................................. 174

8.2.2 DTC Mode Register B (MRB).............................................................................. 175

8.2.3 DTC Source Address Register (SAR)................................................................... 177

8.2.4 DTC Destination Address Register (DAR)........................................................... 177

8.2.5 DTC Transfer Count Register A (CRA) ............................................................... 178

8.2.6 DTC Transfer Count Register B (CRB)................................................................ 179

8.2.7 DTC Enable Registers A to E (DTCERA to DTCERE) ....................................... 180

8.2.8 DTC Control Register (DTCCR) .......................................................................... 181

8.2.9 DTC Vector Base Register (DTCVBR)................................................................ 183

Rev. 4.00 Dec. 15, 2009 Page x of lviii

REJ09B0181-0400

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