R1LV0408CSA-5SC Просмотр технического описания (PDF) - Renesas Electronics

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R1LV0408CSA-5SC

R1LV0408C-C Series 4M SRAM (512-kword ×8-bit)

Renesas Electronics 

R1LV0408C-C Series

Low VCC Data Retention Characteristics

(Ta = −20 to +70°C)

Parameter

Symbol Min Typ Max Unit Test conditions*3

VCC for data retention

VDR

2   V CS# ≥ VCC − 0.2 V, Vin ≥ 0 V

Data

retention

current

−5SC

to +70°C

to +40°C

to +25°C

ICCDR

ICCDR

ICCDR

 8

 0.7*2 3

 0.5*1 3

µA VCC = 3.0 V, Vin ≥ 0 V

µA CS# ≥ VCC − 0.2 V

µA

−7LC

to +70°C

to +40°C

to +25°C

ICCDR

ICCDR

ICCDR

  16 µA

 0.7*2 10 µA

 0.5*1 10 µA

Chip deselect to data retention time

tCDR

Operation recovery time

tR

0

tRC*4 

 ns See retention waveform

 ns

Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.

2. Typical values are at VCC = 3.0 V, Ta = +40°C and specified loading, and not guaranteed.

3. CS# controls address buffer, WE# buffer, OE# buffer, and Din buffer. In data retention mode,

Vin levels (address, WE#, OE#, I/O) can be in the high impedance state.

4. tRC = read cycle time.

Low VCC Data Retention Timing Waveform (CS# Controlled)

tCDR

Data retention mode

tR

VCC

2.7 V

2.2 V

VDR

CS#

0V

CS# ≥ VCC – 0.2 V

Rev.2.00, May.25.2004, page 12 of 12

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