PXA210 Просмотр технического описания (PDF) - Intel

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PXA210

Intel® PXA250 and PXA210 Applications Processors

Intel 

Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210

3.1.1

Functional Signal Definitions

3.1.1.1

PXA250 Signal Pin Descriptions

Signal definitions for the PXA250 applications processor are described in Table 2, “Pin and Signal

Descriptions for the PXA250 Applications Processor” on page 9. The physical characteristics of

the PXA250 applications processor are shown in Figure 2, “PXA250 Applications Processor” on

page 16. The pinout for the PXA250 applications processor is described in Table 3, “PXA250 256-

Lead 17x17mm mBGA Pinout — Ballpad Number Order” on page 17.

Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 1 of 7)

Name

Type

Description

Memory Controller Pins

MA[25:0]

OCZ

Memory address bus. This bus signals the address requested for memory

accesses.

MD[15:0]

ICOCZ Memory data bus. D[15:0] are used for 16-bit data mode.

MD[31:16]

Memory data bus. D[31:16]: These data bits are used for the PXA250 applications

ICOCZ processor 32-bit memories and are not pinned out for the PXA210 applications

processor, 16-bit package option.

nOE

nWE

nSDCS[3:0]

DQM[3:0]

nSDRAS

nSDCAS

SDCKE[0]

SDCKE[1]

OCZ

OCZ

OCZ

OCZ

OCZ

OCZ

OC

OC

Memory output enable. This signal should be connected to the output enables of

memory devices to control their data bus drivers.

Memory write enable. Connect this signal should to the write enables of memory

devices.

SDRAM CS for banks 0 through 3. Connect these signals to the chip select (CS)

pins for SDRAM. nSDCS0 is three-stateable nSDCS1-3 are not

SDRAM DQM for data bytes 0 through 3. Connect these signals to the data output

mask enables (DQM) for SDRAM.

SDRAM RAS. Connect this signal should to the row address strobe (RAS) pins for

all banks of SDRAM.

SDRAM CAS. Connect this signal should to the column address strobe (CAS)

pins for all banks of SDRAM.

SDRAM and/or Synchronous Static Memory clock enable.

Connect SDCKE[0] to the CKE pins of SMROM and SDRAM-timing Synchronous

Flash.

The memory controller provides control register bits for deassertion of each

SDCKE pin.

SDRAM and/or Synchronous Static Memory clock enable.

Connect SDCKE[1] to the SDRAM clock enable pins. It is de-asserted (held low)

during sleep. SDCKE[1] is always deasserted upon reset.

The memory controller provides control register bits for deassertion of each

SDCKE pin.

Datasheet

9

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