AD8611AR Просмотр технического описания (PDF) - Analog Devices
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AD8611AR Datasheet PDF : 20 Pages
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AD8611/AD8612
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V+ 1
8 QA
IN+ 2 AD8611 7 QA
IN– 3 TOP VIEW 6 GND
V– 4 (Not to Scale) 5 LATCH
Figure 4. 8-Lead Narrow Body SOIC Pin Configuration
V+ 1
IN+ 2
IN– 3
V– 4
AD8611
TOP VIEW
(Not to Scale)
8 QA
7 QA
6 GND
5 LATCH
Figure 5. 8-Lead MSOP Pin Configuration
QA 1
QA 2
GND 3
LEA 4
V– 5
INA– 6
INA+ 7
14 QB
AD8612
TOP VIEW
(Not to Scale)
13 QB
12 GND
11 LEB
10 V+
9 INB–
8 INB+
Figure 6. 14-Lead TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
SOIC and
MSOP
TSSOP Mnemonic
1
10
V+
2
IN+
3
IN−
4
5
V−
5
LATCH
6
3, 12
GND
7
1
QA
8
2
QA
14
QB
13
QB
4
LEA
11
LEB
7
INA+
6
INA−
8
INB+
9
INB−
Description
Positive Supply Terminal.
Noninverting Analog Input of the Differential Input Stage.
Inverting Analog Input of the Differential Input Stage.
Negative Supply Terminal.
Latch Enable Input.
Negative Logic Supply
One of Two Complementary Output for Channel A.
One of Two Complementary Output for Channel A.
One of Two Complementary Output for Channel B.
One of Two Complementary Output for Channel B.
Channel A Latch Enable.
Channel B Latch Enable.
Noninverting Analog Input of the Differential Input Stage for Channel A.
Inverting Analog Input of the Differential Input Stage for Channel A.
Noninverting Analog Input of the Differential Input Stage for Channel B.
Inverting Analog Input of the Differential Input Stage for Channel B.
Rev. A | Page 6 of 20
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