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PNX8526

Programmable source decoder with integrated peripherals

Philips Electronics 

Philips Semiconductors

PNX8526

Programmable Source Decoder with Integrated Peripherals

Table 9: IEEE 1394 port

Symbol

Pin Type

PHY_D[7]

B9

I/O

PHY_D[6]

D10 I/O

PHY_D[5]

C9 I/O

PHY_D[4]

A8

I/O

PHY_D[3]

B8

I/O

PHY_D[2]

D9 I/O

PHY_D[1]

C8 I/O

PHY_D[0]

A7

I/O

PHY_CTL[1]

B7

I/O

PHY_CTL[0]

C7 I/O

PHY_LREQ

B5

O

PHY_ISO_N

A6

I

CLK_L1394

D8 I

Description

PHY Data Bit 7. Data is expected on pins 7:0 for 400 MB packets.

PHY Data Bit 6. Data is expected on pins 7:0 for 400 MB packets.

PHY Data Bit 5. Data is expected on pins 7:0 for 400 MB packets.

PHY Data Bit 4. Data is expected on pins 7:0 for 400 MB packets.

PHY Data Bit 3. Data is expected on pins 3:0 for 200 MB packets.

PHY Data Bit 2. Data is expected on pins 3:0 for 200 MB packets.

PHY Data Bit 1. Data is expected on pins 1:0 for 100 MB packets.

PHY Data Bit 0. Data is expected on pins 1:0 for 100 MB packets.

PHY Control Bit 1. Indicates the mode for data on the Din port.

PHY Control Bit 0. Indicates the mode for data on the Din port.

Used by the link to make bus requests and to access PHY registers. This is a serial

bus. A train of pulses is sent on this signal.

Signals which type of isolation mode is used at the PHY-Link interface.

0 = This is 1394-1995 Annex J type isolation. Enables differentiator circuitry.

1 = Direct connection or single capacitor isolation mode. This will disable the

differentiator circuitry.

System clock. 49.152 MHz input

Table 10: Serial communication port (I2C)

Symbol

Pin Type Description

I2C1_SCL

D6 I/O

Serial Communications Port (I2C-bus) Clock

I2C1_SDA

A4 I/O

Serial Communications Port (I2C-bus) Data

I2C2_SCL

H1 I/O

Serial Communications Port (I2C-bus) Clock

I2C2_SDA

K4 I/O

Serial Communications Port (I2C-bus) Data

Table 11: Audio and video interface

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

Pin Type Description

DV_OUT1[9]

DV_OUT1[8]

DV_OUT1[7]

DV_OUT1[6]

DV_OUT1[5]

DV_OUT1[4]

DV_OUT1[3]

DV_OUT1[2]

DV_OUT1[1]

DV_OUT1[0]

DV_OUT2[9]

DV_OUT2[8]

DV_OUT2[7]

M2 O

M1 O

N4 O

N3 O

N1 O

N2 O

P2 O

P1 O

P4 O

P3 O

R2 O

R4 O

R3 O

Digital Video Output1, Bit 9 for primary display channel from AICP

Digital Video Output1, Bit 8 for primary display channel from AICP

Digital Video Output1, Bit 7 for primary display channel from AICP

Digital Video Output1, Bit 6 for primary display channel from AICP

Digital Video Output1, Bit 5 for primary display channel from AICP

Digital Video Output1, Bit 4 for primary display channel from AICP

Digital Video Output1, Bit 3 for primary display channel from AICP

Digital Video Output1, Bit 2 for primary display channel from AICP

Digital Video Output1, Bit 1 for primary display channel from AICP

Digital Video Output1, Bit 0 for primary display channel from AICP

Digital Video Output2, Bit 9 for secondary display channel from AICP

Digital Video Output2, Bit 8 for secondary display channel from AICP

Digital Video Output2, Bit 7 for secondary display channel from AICP

Alternate

Function

9397 750 11715

Preliminary data

Rev. 01 – 6 October 2003

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

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