PNX3000 Просмотр технического описания (PDF) - Philips Electronics

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PNX3000

Analog front end for digital video processors

Philips Electronics 

Philips Semiconductors

Analog front end for digital video

processors

Preliminary specification

PNX3000

horizontal timing pulse that starts just before and ends just

after the horizontal sync pulse of the selected video signal.

To enable detection of the vertical blanking period, the

horizontal pulses must be wider during a number of lines

in the vertical blanking interval.

The clamp signal inside the IC is generated with the help

of the external horizontal timing pulse and the 13.5 MHz

clock. The vertical timing information is used to disable the

black level clamp, so that the black level is not disturbed

by the vertical sync pulse on the video signal. The clamp

pulse for the YUV channel can be derived from the primary

or the secondary HV pulse, and is selected by bus bit

CLPS.

To avoid signal disturbance, it is possible to disable the

black clamps when the horizontal PLL in the digital video

processor is not locked to the selected video signal. This

is done by bus bit CMP for the primary CVBS channel and

bus bit CMS for the secondary CVBS channel.

Special attention is required when the same CVBS input is

selected for primary and secondary CVBS channels.

In this case the black level clamp loop is only closed for the

primary CVBS input. Due to internal offsets this will

normally result in a deviation on the black level of the

digitized secondary CVBS output.

7.10 Data link transmitters

Three serial data links are used for transportation of the

digital video and audio data coming from the ADCs in the

PNX3000 to the digital video processor. The use of serial

data connections results in a considerable reduction in pin

count and the number of connection wires that are needed

between both ICs.

The communication between data link transmitter and data

link receiver consists of two signals, a data signal and a

strobe signal. The two signals together contain the data,

bit-sync and word-sync information. For optimal EMC

performance both data and strobe are low voltage

differential signals. The voltage swing on each wire is

300 mV.

Each data word sent over a data link consists of 44 bits:

4 video samples of 10 bits each, 2 audio bits and

2 word-sync bits. The word clock is 13.5 MHz. The data

rate on each of the three data links is 594 Mbit/s.

Table 2 shows which video signals are sent to the digital

video processor for both data link modes. In the standard

mode up to three video channels plus one sound IF signal

are digitized and transferred simultaneously over the data

links.

The distance between both ICs that are connected via the

data link must not be larger than about 10 centimetres.

The two wires for each differential signal should be paired

in the layout of the printed-circuit board.

7.11 I2C-bus transceiver

The slave address of the I2C-bus transceiver in the

PNX3000 has two possible values, selected via the

ADR pin. The maximum bus clock frequency is 400 kHz,

and the voltage swing of SCL and SDA can be 3.3 V

or 5 V. The I2C-bus transceiver also has a hardwired IRQ

output (open drain and LOW-active) for interruption of the

microprocessor when the value of an important status bit

in status byte 0 changes. The IRQ signal is maskable with

register 0FH.

7.12 Power supply circuit

An internal bandgap circuit generates a stable voltage of

1.25 V. This voltage is multiplied to a reference voltage of

2.3 V, and a digital supply voltage of 2.5 V. These two

voltages must be decoupled by external capacitors.

A 1/2VP reference voltage for the audio ADCs also requires

an external decoupling capacitor. The PNX3000 contains

two voltage regulators to supply the SDACs that are used

in the digital video processor. Each regulator requires a

few external components (one transistor, two resistors and

a decoupling capacitor). The output voltage is adjustable

between 1.25 V and 3.3 V by selection of external

resistors values.

7.13 East-west interface

The PNX3000 contains a voltage to current converter that

serves as the interface between the voltage output of the

digital video processor and the current input of the

east-west stage of the vertical deflection amplifier

(TDA8358). The transconductance is determined by the

value of an external resistor.

2004 Oct 04

14

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