PLL102-108XC Просмотр технического описания (PDF) - PhaseLink Corporation
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PLL102-108XC Datasheet PDF : 10 Pages
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PLL102-108
Programmable DDR Zero Delay Clock Driver
PIN DESCRIPTIONS
Name
VDD
GND
AVDD
AGND
CLKT(0:9)
CLKC(0:9)
CLK_INT
N/C
FB_OUTT
FB_INT
SDATA
SCLK
Number
Type
Description
4,11,15,21,28,34,
38,45
P
2.5V power supply.
1,7,8,18,24,
25,31,41,42,48
P Ground
16
P Analog power supply (2.5V).
17
P Analog ground.
3,5,10,20,22,46,
44,39,29,27
I “True” clocks of differential pair outputs.
2,6,9,19,23,47,
43,40,30,26
I “Complementary” clocks of differential pair outputs.
13
I Single-ended 3.3V tolerant input.
14,32,36
Not connected.
33
O
“True” feedback output. Dedicated for external feedback. It switches at the
same frequency as the CLK_INT.
35
I
“True” feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
37
B
Serial data input for serial interface port.
12
I
Functionality
AVDD
2.5V (Nom)
2.5V (Nom)
GND
GND
INPUTS
CLK_INT
L
H
L
H
CLK_INC
H
L
H
L
CLKT
L
H
L
H
OUTPUTS
CLKC
H
L
H
L
FB_OUTT
L
H
L
H
PLL State
On
On
Bypass/Off
Bypass/Off
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/29/02 Page 2
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