HI20203(2000) Просмотр технического описания (PDF) - Intersil
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HI20203 Datasheet PDF : 10 Pages
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HI20203
Pin Descriptions
28 PIN SOIC
28
PIN NAME
AVSS
Analog Ground
PIN DESCRIPTION
Detailed Description
The HI20203 is an 8-bit, current-output D/A converter. The
converter has 10 data bits but yields 8-bit performance.
Architecture
The HI20203 is a combined R2R/segmented current source
design. The 6 least significant bits of the converter are derived by
a traditional R2R network to binary weight the 1mA current
sources. The upper 4 most significant bits are implemented as
segmented or thermometer encoded current sources. The
encoder converts the incoming 4 bits to 15 control lines to enable
the most significant current sources. The thermometer encoder
will convert binary to individual control lines. See Table 1.
MSB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TABLE 1. THERMOMETER ENCODER
BIT 6
0
BIT 5
0
BIT 4
0
THERMOMETER CODE
1 = ON, 0 = OFF
I15 - I0
000 0000 0000 0000
0
0
1
000 0000 0000 0001
0
1
0
000 0000 0000 0011
0
1
1
000 0000 0000 0111
1
0
0
000 0000 0000 1111
1
0
1
000 0000 0001 1111
1
1
0
000 0000 0011 1111
1
1
1
000 0000 0111 1111
0
0
0
000 0000 1111 1111
0
0
1
000 0001 1111 1111
0
1
0
000 0011 1111 1111
0
1
1
000 0111 1111 1111
1
0
0
000 1111 1111 1111
1
0
1
001 1111 1111 1111
1
1
0
011 1111 1111 1111
1
1
1
111 1111 1111 1111
01 1111 1111 to 10 0000 0000. But in the HI20203 the glitch
is moved to the 00 0001 1111 to 11 1110 0000 transition. This
is achieved by the split R2R/segmented current source
architecture. This decreases the amount of current switching
at any one time and makes the glitch practically constant over
the entire output range. By making the glitch a constant size
over the entire output range this effectively integrates this
error out of the end application.
In measuring the output glitch of the HI20203 the output is
terminated into a 75Ω load. The glitch is measured at the
major carry’s throughout the DACs output range.
The glitch energy is calculated by measuring the area under
the voltage-time curve. Figure 7 shows the area considered
as glitch when changing the DAC output. Units are typically
specified in picoVolt/seconds (pV/s).
HI20203
(20) IOUT
34MHz
SCOPE
LOW PASS
FILTER
75Ω
50Ω
FIGURE 6. HI20203 GLITCH TEST CIRCUIT
A (mV)
GLITCH ENERGY = (a x t)/2
The architecture of the HI20203 is designed to minimize glitch
while providing a manufacturable 10-bit design that does not
require laser trimming to achieve good linearity.
Glitch
Glitch is caused by the time skew between bits of the
incoming digital data. Typically the switching time of digital
inputs are asymmetrical meaning that the turn off time is
faster than the turn on time (TTL designs). In an ECL system
where the logic levels switch from one non-saturated level to
another, the switching times can be considered close to
symmetrical. This helps to reduce glitch in the D/A. Unequal
delay paths through the device can also cause one current
source to change before another. To minimize this the Intersil
HI20203 employs an internal register, just prior to the current
sources, that is updated on the clock edge. Lastly the worst
case glitch usually happens at the major transition i.e.,
t (ns)
FIGURE 7. GLITCH ENERGY
Setting Full Scale
The Full Scale output voltage is set by the Voltage Refer-
ence pin (27). The output voltage performance will vary as
shown in Figure 2.
The output structure of the HI20203 can handle down to a
75Ω load effectively. To drive a 50Ω load Figure 8 is
6
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