HD74HC299 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HD74HC299

8-bit Universal Shift/Storage Register (with 3-state outputs)

Hitachi -> Renesas Electronics 

HD74HC299

Function Table

Inputs

Function Output

Select Control

Serial Inputs/Outputs

Outputs

Mode Clear S1 S0 G1† G2† Clock SL SR A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH QA’ QH’

Clear L

XL L L X

XXL L L L L L L L L L

L

L XL L X

XXL L L L L L L L L L

Hold H

LLLL X

X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0

H

XXL L L

X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0

Shift H

L HL L

XHH

QAn QBn QCn QDn QEn QFn QGn H

QGn

Right H

L HL L

XL L

QAn QBn QCn QDn QEn QFn QGn L

QGn

Shift H

HL L L

H X QBn QCn QDn QEn QFn QGn QHn H

QBn H

Left H

HL L L

L X QBn QCn QDn QEn QFn QGn QHn L

QBn L

Load H

HHXX

XXa b c d e f

gh ah

Notes: 1. a to h; the level of steady-state input at inputs A through H, respectively. These data are

loaded into the flip-flop outputs are isolated from the input/output terminals.

2. QA0 to QH0; the level of QA through QH, respectively, before the indicated steady-state input

conditions were established.

3. QAn to QHn; the level of QA through QH, respectively, before the most-recent

clock.

transition of the

4. † = ; When one or both output controls are high the eight input/output terminals are desabled to

the high-impedance state, however, sequential operation or clearing of the register is not

affected.

5. When clear is low, outputs of QA’ and QH’ are low, in spite of other inputs.

2

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