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W83196S-14

100 MHZ CLOCK FOR BX CHIPSET (2 CHIP)

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Preliminary W83196S-14

9. OPERATION OF DUAL FUCTION PINS

Pin13 is dual function pins and are used for selecting different functions in this device (see Pin

description). During power up, these pins are in input mode (see Figure 1), therefore, and are

considered input select pins. When VDD reaches 2.5V, the logic level that is present on these pins are

latched into their appropriate internal registers. Once the correct information are properly latched,

these pins will change into output pins and will be pulled low by default. At the end of the power up

timer (within 3 ms) outputs starts to toggle at the specified frequency.

2.5V

VDD

#13 48/MODE*

Output

tri-state

All other clocks

Input

Output

tri-state

Output

pull-low

Within 3 mS

Output

Output

pull-low

Each of these pins are a large pull-up resistor ( 250 KΩ @3.3V ) inside. The default state will be logic

1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these

dual function pins. Under these conditions, an external 10 KΩ resistor is recommended to be

connected to VDD if logic 1 is expected. The same 10 KΩ connection to ground if a logic 0 is desired.

The 10 KΩ resistor should be place before the serious terminating resistor. Note that these logic will

only be latched at initial power on.

If optional EMI reducing capacitor are needed, they should be placed as close to the series

terminating resistor as possible and after the series terminating resistor. These capacitor has typical

values ranging from 4.7 pF to 22 pF.

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