W83194R-37 Просмотр технического описания (PDF) - Winbond

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W83194R-37

100 MHZ AGP CLOCK FOR VIA CHIPSET

Winbond 

Preliminary W83194R-37/-58

Each of these pins are a large pull-up resistor (250 KΩ @3.3V) inside. The default state will be logic

1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these

dual function pins. Under these conditions, an external 10 KΩ resistor is recommended to be

connected to VDD if logic 1 is expected. Otherwise, the 10 KΩ resistor is connected to ground if a

logic 0 is desired. The 10 KΩ resistor should be place before the serious terminating resistor. Note

that these logic will only be latched at initial power on.

If optional EMI reducing capacitor are needed, they should be placed as close to the series

terminating resistor as possible and after the series terminating resistor. These capacitor has typical

values ranging from 4.7 pF to 22 pF.

VDD

Device

Pin

Series

10 KΩ Terminating

Resistor

Clock

Trace

10 KΩ

EMI

Reducing

Cap

Ground

Optional

Ground

Programming Header

VDD Pad

10 KΩ

Device

Pin

Ground Pad

Series

Terminating

Resistor

Clock

Trace

EMI

Reducing

Cap

Optional

Ground

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