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PI6C185-02B

Precision 1-7 Clock Buffer

Pericom Semiconductor 

PI6C185-02B

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Output

Buffer

Test

Point

Test Load

3.3V

Clocking

Interface

(TTL)

2.4

1.5

0.4

tSDKH

tSDKP

tSDRISE

tSDFALL

tSDKL

Input

Waveform

1.5V

tplh

Output

Waveform

1.5V

1.5V

tphl

1.5V

Figure 1. Clock Waveforms

Minimum and Maximum Expected Capacitive Loads

Clock Min Load Max Load Units

Notes

SDRAM

15

20

pF SDRAM DIMM Specification

Notes:

1. Maximum rise/fall times are guaranteed at maximum specified load.

2. Minimum rise/fall times are guaranteed at minimum specified load.

3. Rise/fall times are specified with pure capacitive load as shown.

Testing is done with an additional 500Ω resistor in parallel.

Design Guidelines to Reduce EMI

1. Place RS series resistors and CI capacitors as close as possible to the respective clock pins. Typical

value for CI is 10pF. RS Series resistor value can be increased to reduce EMI provided that the rise

and fall time are still within the specified values.

2. Minimize the number of “vias” of the clock traces.

3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing

clock traces from plane to plane (refer to rule #2).

4. Position clock signals away from signals that go to any cables or any external connectors.

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PS8469 05/03/00

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