SN74LS299H Просмотр технического описания (PDF) - ON Semiconductor
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SN74LS299H Datasheet PDF : 8 Pages
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S1 19 S0 1
SN74LS299
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC S1 Ds7 Q7 I/O7 I/O5 I/O3 I/O1 CP DS0
20 19 18 17 16 15 14 13 12 11
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1 2 3 4 5 6 7 8 9 10
S0 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 MR GND
PIN NAMES
CP
DS0
DS7
I/On
OE1, OE2
Q0, Q7
MR
S0, S1
Clock Pulse (Active Positive–Going Edge) Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Parallel Data Input or
Parallel Output (3–State)
3–State Output Enable (Active LOW) Inputs
Serial Outputs
Asynchronous Master Reset (Active LOW) Input
Mode Select Inputs
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
0.5 U.L.
10 U.L.
0.5 U.L.
1 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
0.25 U.L.
5 U.L.
0.25 U.L.
0.5 U.L.
LOGIC DIAGRAM
DS0
11
12
CLOCK
Q0 8
MR
9
2
OE1
OE2 3
18
DS7
D CK
CLR
Q
7
I/O0
D
CLR
CK
Q
13
I/O1
D
CLR
CK
Q
6
I/O2
D CK
CLR
Q
14
I/O3
D CK
CLR
Q
5
I/O4
D CK
CLR
Q
15
I/O5
D CK
CLR
Q
4
I/O6
D CK
CLR
Q
17
Q7
VCC = PIN 20
16
GND = PIN 10
= PIN NUMBERS
I/O7
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