MM74HC597CW Просмотр технического описания (PDF) - Fairchild Semiconductor

Номер в каталоге

Компоненты Описание

Список матч

MM74HC597CW

8-Bit Shift Registers with Input Latches

Fairchild Semiconductor 

January 1988

Revised August 2000

MM74HC597

8-Bit Shift Registers with Input Latches

General Description

This high speed register utilizes advanced silicon-gate

CMOS technology. It has the high noise immunity and low

power consumption of standard CMOS integrated circuits,

as well as the ability to drive 10 LS-TTL loads.

The MM74HC597 comes in a 16-pin package and consists

of an 8-bit storage latch feeding a parallel-in, serial-out

8-bit shift register. Both the storage register and shift regis-

ter have positive-edge triggered clocks. the shift register

also has direct load (from storage) and clear inputs.

The 74HC logic family is speed, function, and pin-out com-

patible with the standard 74LS logic family. All inputs are

protected from damage due to static discharge by internal

diode clamps to VCC and ground.

Features

s 8-bit parallel storage register inputs

s Wide operating voltage range: 2V–6V

s Shift register has direct overriding load and clear

s Guaranteed shift frequency: DC to 30 MHz

s Low quiescent current: 80 µA maximum

Ordering Code:

Order Number Package Number

Package Description

MM74HC597M

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

MM74HC597SJ

M16D

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC597N

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Truth Table

Top View

RCK SCK SLOAD SCLR

Function

↑X

X

X Data Loaded to input latches

↑X

L

Data loaded from inputs to

H

shift register

No

Data transferred from

clock X

L

H input latches to shift

edge

register

Invalid logic, state of

XX

L

L shift register indeterminate

when signals removed

XX

H

L Shift register cleared

X↑

H

Shift register clocked

H

Qn = Qn−1, Q0 = SER

© 2000 Fairchild Semiconductor Corporation DS005343

www.fairchildsemi.com

Share Link: