SY100S341 Просмотр технического описания (PDF) - Micrel

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SY100S341

8-BIT SHIFT REGISTER

Micrel 

Micrel, Inc.

8-BIT SHIFT

REGISTER

SY100S341

SY100S341

FEATURES

DESCRIPTION

s Max. shift frequency of 600MHz

s Max. Clock to Q delay of 1200ps

s IEE min. of –150mA

s Industry standard 100K ECL levels

s Extended supply voltage option:

VEE = –4.2V to –5.5V

s Voltage and temperature compensation for improved

noise immunity

s Internal 75KΩ input pull-down resistors

s 70% faster than Fairchild 300K at lower power

s Function and pinout compatible with Fairchild F100K

s Available in 24-pin CERPACK and 28-pin PLCC

packages

The SY100S341 offer eight D-type, edge-triggered flip-

flops with both individual inputs for parallel operation as

well as serial inputs for bidirectional shifting, and are

designed for use in high-performance ECL systems. Data

is clocked into the flip-flops on the rising edge of the clock.

The mode of operation is selected by two Select inputs

(S0, S1) which determine if the device performs a shift, hold

or parallel entry function, as described in the Truth Table.

The inputs on these devices have 75KΩ pull-down resistors.

PIN NAMES

Label

CP

S0 — S1

D0 — D7

P0 — P7

Q0 — Q7

VEES

VCCA

Function

Clock Pulse Input

Select Inputs

Serial Inputs

Parallel Inputs

Data Outputs

VEE Substrate

VCCO for ECL Outputs

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

1

Rev.: H

Amendment: /0

Issue Date: March 2006

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