BA823F(2009) Просмотр технического описания (PDF) - ROHM Semiconductor
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BA823F Datasheet PDF : 9 Pages
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BA823F
●Block diagram
STROBE INPUT S 1
DATA INPUT D4 15
SHIFT PULSE C 2
Technical Note
Ō0 Ō1 Ō2 Ō3 Ō4 Ō5
Ō6
Ō7
12
11
10
9
8
7
6
5
16 VCC
3 DATA OUTPUT DO
13 GND1
4 GND2
14 GND
(Dig)
●Pin descriptions
Pin No. Pin Name
2 SHIFT PULSE
15
DATA INPUT
1
STROBE
12
OUTPUT
11
OUTPUT
10
OUTPUT
9
OUTPUT
8
OUTPUT
7
OUTPUT
6
OUTPUT
5
OUTPUT
3 DATA OUTPUT
16
VCC
13
GND
4
GND
14
GND
Symbol
C
D1
S
Ō0
Ō1
Ō2
Ō3
Ō4
Ō5
Ō6
Ō7
Do
VCC
GND1
GND2
GND(Dig)
Function
Shift pulse of shift register
Data input of shift register is stored during the shift pulse rise time.
When “1” is effective, the content of shift register is outputted.
“0” is effective when the content of register is “1” on the 1st bit is outputted.
“0” is effective when the content of register is “1” on the 2nd bit is outputted.
“0” is effective when the content of register is “1” on the 3rd bit is outputted.
“0” is effective when the content of register is “1” on the 4th bit is outputted.
“0” is effective when the content of register is “1” on the 5th bit is outputted.
“0” is effective when the content of register is “1” on the 6tht bit is outputted.
“0” is effective when the content of register is “1” on the 7tht bit is outputted.
“0” is effective when the content of register is “1” on the 8th bit is outputted.
Data having passed through the output circuit of Ō7 becomes the input of the next stage
5.0V .is used normally (±10%)
Especially, GND of the output circuit of Ō 0~ Ō 3
Especially, GND of the output circuit of Ō 4~ Ō7
Especially, GND of the logic circuit
●Description of operation
BA823 is configured internally as shown in the block diagram. Terminals of clock C, data D1, and strobe S are used as input.
Data input is synchronized with the clock, read serially during the rise time and latched at the rise time edge of the shifted
shift register. The content of the set shift register appears on the output terminal of Ō0~ Ō7 when the strobe is input, as
shown in the time chart of Fig.5. Pulse width is the same as that of the strobe input pulse.
Data output terminal D0, is a terminal used for cascade connection of the IC, where the output of the final stage of the shift
register has appeared, and is connected to the next data input terminal D1. In this case, when the clock and the strobe are
used in conjunction, output terminal can be increased by 8 bits at a time.
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3/8
2009.06 - Rev.A
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