ST62T20CB6 Просмотр технического описания (PDF) - STMicroelectronics
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ST62T20CB6
STMicroelectronics
ST62T20CB6 Datasheet PDF : 70 Pages
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ST62T08C/T09C ST62T10C/T20C/E20C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T08C,T09C,T10C,T20C and ST62E20C
devices are low cost members of the ST62xx 8-bit
HCMOS family of microcontrollers, which is target-
ed at low to medium complexity applications. All
ST62xx devices are based on a building block ap-
proach: a common core is surrounded by a
number of on-chip peripherals.
The ST62E20C is the erasable EPROM version of
the ST62T08C,T09C,T10C and T20C device,
which may be used to emulate the
ST62T08C,T09C,T10C and T20C device, as well
as the respective ST6208C,09C,10C,20C ROM
devices.
OTP and EPROM devices are functionally identi-
cal. The ROM based versions offer the same func-
Figure 1. Block Diagram
tionality selecting as ROM options the options de-
fined in the programmable option bytes of the
OTP/EPROM versions.
OTP devices offer all the advantages of user pro-
grammability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
These compact low-cost devices feature a Timer
comprising an 8-bit counter and a 7-bit program-
mable prescaler,an 8-bit A/D Converter with up to
8 analog inputs and a Digital Watchdog timer,
making them well suited for a wide range of auto-
motive, appliance and industrial applications.
TEST/VPP
NMI
TEST
8-BIT
A/D CONVERTER
INTERRUPT
PORT A
PORT B
PA0..PA3 (20mA Sink)
PB0..PB7 / Ain (*)
PROGRAM
MEMORY
:
1036 Bytes
(ST62T08C,T09C)
1836 Bytes
(ST62T10C)
3884 Bytes
(ST62T20C, E20C)
DATA ROM
USER
SELECTABLE
DATA RAM
64 Bytes
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
8 BIT CORE
POWER
SUPPLY
OSCILLATOR
RESET
TIMER
DIGITAL
WATCHDOG
TIMER
VDD VSS OSCin OSCout RESET
(*) Analog input availability depend on versions
4/70
92
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