PE9704 Просмотр технического описания (PDF) - Peregrine Semiconductor Corp.

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PE9704

3.0 GHz Integer-N PLL for Rad Hard Applications

Peregrine Semiconductor Corp. 

PE9704

Advance Information

Figure 3. Serial Interface Mode Timing Diagram

DATA

E_WR

tEC

CLOCK

S_WR

tDSU

tDHLD

tClkH

tClkL

tCE

tCWR

tPW

tWRC

Enhancement Register

The functions of the enhancement register bits are shown below. All bits are active high. Operation is

undefined if more than one output is sent to DOUT.

Table 9. Enhancement Register Bit Functionality

Bit Function

Bit 0

Reserved**

Bit 1

Reserved**

Bit 2

Bit 3

fp output

Power down

Bit 4

Counter load

Bit 5

MSEL output

Bit 6

Bit 7

fc output

Reserved**

** Program to 0

Description

Drives the M counter output onto the DOUT output.

Power down of all functions except programming interface.

Immediate and continuous load of counter programming.

Drives the internal dual modulus prescaler modulus select (MSEL) onto the DOUT output.

Drives the R counter output onto the DOUT output

PEREGRINE SEMICONDUCTOR CORP.  | http://www.peregrine-semi.com

Copyright  Peregrine Semiconductor Corp. 2003

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