PE42612-00 Просмотр технического описания (PDF) - Peregrine Semiconductor Corp.
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PE42612-00 Datasheet PDF : 4 Pages
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PE42612
Product Brief
Figure 3. Pin Configuration (Ball-Side Up)
N/C ANT
TX1 10 11 12
1 RX1
GND 9
TX2 8
PE42612
Die
2 GND
3 RX2
GND 7
6
5
4
V1
VDD V2
Table 4. Pin Descriptions
Pin No.
15
2
35
4
5
6
7
85
9
105
11
125
Pin Name
RX1
GND
RX2
V1
V2
VDD
GND
TX2
GND
TX1
N/C
ANT
Description
RF I/O – RX1
Ground
RF I/O – RX2
Switch control input, CMOS logic level
Switch control input, CMOS logic level
Supply
Ground
RF I/O - TX2
Ground
RF I/O - TX1
No Connect – Pin to be connected to an
electrically isolated low capacitance pad
RF Common – Antenna Input
Note:
5. Blocking capacitors needed only when non-zero DC
voltage present.
Table 5. Truth Table
Path
ANT - RX1
ANT - RX2
ANT - TX1
ANT - TX2
V2
V1
0
0
0
1
1
0
1
1
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 6. Ordering Information
Order Code
Die ID
PE42612-90 (Unitive)
C9817_1
PE42612-91 (FCI)
C9817_1
PE42612-00
C9817_1
Description
PE42612-DIE-D
PE42612-DIE-D
PE42612-DIE-1H
Package
Film Frame
Film Frame
Evaluation Kit
Shipping Method
Wafer (Gross Die / Wafer Quantity)
Wafer (Gross Die / Wafer Quantity)
1 / Box
Document No. 70-0217-01 │ www.psemi.com
Contact sales@psemi.com for full version of datasheet
©2006 Peregrine Semiconductor Corp. All rights reserved.
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