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PDI1394P25

1-port 400 Mbps physical layer interface

Philips Electronics 

Philips Semiconductors

1-port 400 Mbps physical layer interface

Preliminary data

PDI1394P25

Name

PLLGND

PLLVDD

Pin Type

LQFP

LFBGA

I/O

Pin

Ball

Numbers Numbers

Supply

57, 58

D3, E1

—

Supply

56

D1, D4

—

RESET

CMOS 5 V tol 53

C1

I

R0

Bias

40

D5

—

R1

41

A4

SYSCLK

CMOS

2

H2

O

TEST0

CMOS

29

C8

I

TESTM

CMOS

27

D7

I

TPA0+

Cable

37

B5

I/O

TPA0–

Cable

36

B6

I/O

TPB0+

Cable

35

C6

I/O

TPB0–

Cable

34

A7

I/O

TPBIAS0

Cable

38

A6

I/O

XI

Crystal

59

E2

—

XO

60

E3

Description

PLL circuit ground terminals. These terminals should be tied together to

the low impedance circuit board ground plane.

PLL circuit power terminals. A combination of high frequency decoupling

capacitors near each terminal are suggested, such as paralleled 0.1 µF

and 0.001 µF. These supply terminals are separated from DVDD and

AVDD internal to the device to provide noise isolation. They should be

tied at a low impedance point on the circuit board.

Logic reset input. Asserting this terminal low resets the internal logic. An

internal pull-up resistor to VDD is provided so only an external

delay capacitor is required for proper power-up operation. For more

information, refer to Section 17.2. This input is otherwise a standard

Schmitt logic input, and can also be driven by an open-drain type driver.

Current setting resistor pins These pins are connected to an external

resistance to set the internal operating currents and cable driver output

currents. A resistance of 6.34 kΩ ±1% is required to meet the IEEE

1394–1995 Std. output voltage limits.

System clock output. Provides a 49.152 MHz clock signal, synchronized

with data transfers, to the LLC.

Test control input. This input is used in manufacturing tests of the

PDI1394P25. For normal use, this terminal should be tied to GND.

Test control input. This input is used in manufacturing tests of the

PDI1394P25. For normal use, this input may be tied to VDD (for

compatibility with other vendors’ pin-compatible PHY chips) or to PHY

GND (when a PDI1394P25 is an alternate device).

Twisted-pair cable A differential signal terminals. Board traces from each

pair of positive and negative differential signal terminals should be kept

matched and as short as possible to the external load resistors and to

the cable connector.

Twisted-pair cable B differential signal terminals. Board traces from each

pair of positive and negative differential signal terminals should be kept

matched and as short as possible to the external load resistors and to

the cable connector.

Twisted-pair bias output. This provides the 1.86 V nominal bias voltage

needed for proper operation of the twisted-pair cable drivers and

receivers, and for signaling to the remote nodes that there is an active

cable connection. These terminals must be decoupled with a

0.3 µF–1 µF capacitor to ground.

Crystal oscillator inputs. These terminals connect to a 24.576 MHz

parallel resonant fundamental mode crystal. The optimum values for the

external shunt capacitors are dependent on the specifications of the

crystal used. Can also be driven by an external clock generator (leave

XO unconnected in this case and start supplying the external clock

before resetting the PDI1394P25). For more information, refer to

Section 17.5

2001 Sep 06

7

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