PCD5041 Просмотр технического описания (PDF) - Philips Electronics
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PCD5041 Datasheet PDF : 28 Pages
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Philips Semiconductors
DECT burst mode controller
4 BLOCK DIAGRAM
Objective specification
PCD5041
handbook, full pagewidth
to CODEC/
Highway
3-wire synthesizer
interface
Rx/Tx data
8051/68000
interface
PCD5041
DECT
BURST MODE
CONTROLLER
TIMING, CONTROL,
CLOCK
GENERATION
SPEECH
INTERFACE
internal
bus
DATA MEMORY
2 kbyte RAM
RF INTERFACE
PROGRAMMABLE
COMMUNICATION
CONTROLLER (PCC)
MICROCONTROLLER
INTERFACE
PCC
PROGRAM MEMORY
4 kbyte ROM
Fig.1 Block diagram.
MBH705
5 PINNING (see Figs 2 and 3)
SYMBOL
AD0 to AD7
ALE
CS
A8 to A10
VDD1
PROC_CLK
VSS1
XTAL1
XTAL2
VSS2
RESET_OUT
RD
WR
RDY
PIN
TYPE(2)
QFP64 LQFP80(1)
DESCRIPTION
1 to 8 80, 1, and I/O address/Data bus
3 to 7
9
9
I
address latch enable
10
11
I
chip select (active LOW)
13 to 11 14 to 12
I
address bus
14
15
P positive supply 1
15
16
O microcontroller clock; programmable from fCLK/64 to fCLK,
where fCLK is the crystal oscillator frequency
16
17
P negative supply 1
17
20
I
crystal oscillator input
18
21
O crystal oscillator output
19
22
P negative supply
20
23
O watchdog timer output; intended to reset the external
microcontroller when expired
21
24
I
read (active LOW)
22
25
I
write (active LOW)
23
26
O ready signal (active LOW), to initiate wait states in the
microcontroller (open drain)
1996 Oct 31
4
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