74F166 Просмотр технического описания (PDF) - Philips Electronics

Номер в каталоге

Компоненты Описание

Список матч

74F166

8-bit bidirectional universal shift register

Philips Electronics 

Philips Semiconductors

8-bit bidirectional universal shift register

Product specification

74F166

FEATURES

• High impedance NPN base inputs for reduced loading

(20µA in high and low states)

• Synchronous parallel to serial applications

• Synchronous serial data input for easy expansion

• Clock enable for ”do nothing” mode

• Asynchronous master reset

• Expandable to 16 bits in 8–bit increments

• Industrial temperature range available (–40°C to +85°C)

DESCRIPTION

The 74F166 is a high speed 8–bit shift register that has fully

synchronous serial parallel data entry selected by an active

low parallel enable (PE) input. When the PE is low one setup

time before the low–to–high clock transition, parallel data is

entered into the register.

When PE is high, data is entered into internal bit position Q0

from serial data input (Ds), and the remaining bits are shifted

one place to the right (Q0 → Q1 → Q2, etc.) with each

positive going clock transition.

For expansion of the register in parallel to serial converters,

the Q7 output is connected to the Ds input of the succeeding

stage. The clock input is gated OR structure which allows

one input to be used as an active–low clock enable (CE)

input. The pin assignment for the CP and CE inputs is

arbitrary and can be reversed for layout convenience. The

low–to–high transition of CE input should only take place

while the CP is high for predictable operation. A low on the

master reset (MR) input overrides all other inputs and clears

the register asynchronously, forcing all bit positions to a low

state.

TYPE

74F166

TYPICAL fmax

175MHz

TYPICAL SUPPLY CUR-

RENT( TOTAL)

50mA

ORDERING INFORMATION

DESCRIPTION

16–pin plastic DIP

16–pin plastic SO

COMMERCIAL RANGE

VCC = 5V ±10%,

Tamb = 0°C to +70°C

N74F166N

N74F166D

ORDER CODE

INDUSTRIAL RANGE

VCC = 5V ±10%,

Tamb = –40°C to +85°C

I74F166N

I74F166D

PKG DWG #

SOT38-4

SOT109-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

D0 – D7

Parallel data inputs

Ds

Serial data input (shift right)

CP

Clock input (active rising edge)

CE

Clock enable input (active low)

PE

Parallel enable input (active low)

MR

Master reset input (active low)

Q7

Data output

Note to input and output loading and fan out table

1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.

74F (U.L.) HIGH/

LOW

1.0/0.033

2.0/0.066

1.0/0.033

1.0/0.033

1.0/0.033

2.0/0.066

50/33

LOAD VALUE HIGH/

LOW

20µA/20µA

40µA/40µA

20µA/20µA

20µA/20µA

20µA/20µA

40µA/40µA

1.0mA/20mA

Feb. 14, 1991

2

853–0349 01718

Share Link: