MP8820AQ Просмотр технического описания (PDF) - Exar Corporation

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MP8820AQ

8-Bit Analog-to-Digital Converter with an 8-Channel MUX

Exar Corporation 

MP8820

tWR

AIN1

AIN2

tMSU

tAP

AIN8

Figure 5. Analog Timing Diagram

clock phase φc. The voltage stored on the capacitor is then

equal to VBAL + (VIN – VTAP). This voltage will force the inverter

high or low and the result is latched.

VIN

φS

VTAP

φC C1

φS

φC

Latch

Figure 6. Comparator Block Diagram

Inside the ADC is a series of comparators that sample the

analog input and compare it against a resistor tap voltage. A

state machine generates the internal clocks necessary to con-

trol the comparators, φc (CLK high) and φs (CLK low = sample).

See Figure 6. The rising edge of the CLK input marks the end of

the sampling phase, φs. On φs, the analog input voltage is

sampled and stored across capacitor C1. The switches con-

trolled by φs are opened prior to the compare which is done on

The analog to digital conversion happens in four phases.

During the first phase, the analog input is sampled. During the

second phase, this input is compared against the reference lad-

der to determine the MSBs. After the MSBs are determined, a

subrange is set for phase three, the conversion of the LSBs.

Once all the bits have been derived, the MP8820 performs a

correction. The valid data is then ready at the output. The timing

diagram is shown in Figure 7.

Sample

φSN

φSN+1

Compare

MSBs

Compare

LSBs

φCMSBs

φCLSBs

Correction

φCORR

Data

Data Sample N-1

Data Sample N

Figure 7. Internal ADC Timing Diagram

The input mux operates as a standard 8 to 1 decoder. One of ter a time equal to tAP following the rising edge of WR. The ad-

eight analog inputs is selected depending on the condition of the dress should be held constant for at least 150 ns before the ris-

address pins A0, A1, and A2. The mux can change address af- ing edge of WR.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Function

WR

XINT

A0

A1

A2

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Start AIN tracking

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Sample AIN

Start Convert

↓

1

X

X

X

↑

1

X

X

X

↑

1

X

X

X

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Conversion Complete

1

↓

X

X

X

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Enable Output Data

X

0

X

X

X

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Select Input AIN1

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Select Input AIN2

Select Input AIN3

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Select Input AIN4

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Select Input AIN5

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Select Input AIN6

Select Input AIN7

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Select Input AIN8

X

X

0

0

0

X

X

0

0

1

X

X

0

1

0

X

X

0

1

1

X

X

1

0

0

X

X

1

0

1

X

X

1

1

0

X

X

1

1

1

Table 2. Truth Table

Rev. 1.00

7

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