MB40C318V Просмотр технического описания (PDF) - Fujitsu
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MB40C318V Datasheet PDF : 16 Pages
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MB40C318V
s PIN DESCRIPTION
Pin No.
3, 9, 13, 45
16, 43
27
4, 7, 12, 44
18, 41
33 to 40
19 to 26
11
14
10
15
28
29
32
31
30
42
17
8
2
1
48
46
47
6
5
Symbol
AVDD
DVDD
DVDDI
AVSS
DVSS
DA7 to DA0
DB7 to DB0
CE
OE
CKSEL
DSEL
RESET
CLKEP
CLKEN
CLKA
CLKB
CLKOA
CLKOB
VINA
VR1
VR2
VR3
VRT
VREFT
VRB
VREFB
Description
Analog power supply (+3.3 V)
Digital power supply (+3.3 V)
Digital power supply for digital input (+5.0 V)
Analog power supply ground pin (0 V)
Digital power supply ground pin (0 V)
Digital output pin (Port A) DA7: MSB, DA0: LSB
Digital output pin (Port B) DB7: MSB, DB0: LSB
Power down at CE input “H” (internal pull-up resistor)
Digital output (Both Port A, B) and clock output (CLKOA, CLKOB) are high
impedance at OE input “H” .
Mode of operation setting input pin (Refer to s MODE SETTING)
Dividing circuit reset input pin (See s TIMING DIAGRAM 2, 3)
Differential clock (positive-phase) input pin (max 140 MHz)
PECL level
Differential clock (negative-phase) input pin (max 140 MHz)
Two-phase clock (A ch) input pin (max 70 MHz)
Two-phase clock (B ch) input pin (max 70 MHz)
TTL level
Clock output pin (See s TIMING DIAGRAM 1 to 4)
Clock output pin (See s TIMING DIAGRAM 1 to 4)
Analog input pin
Input range is VRT to VRB (0 V to 3.0 V: 2 Vp-p)
Reference 1/4 voltage output pin (Add 0.1 µF for AVSS)
Reference 1/2 voltage output pin (Add 0.1 µF for AVSS)
Reference 3/4 voltage output pin (Add 0.1 µF for AVSS)
Reference voltage input pin on top side
Reference voltage output pin
By connecting to VRT, 0.9 × AVDD (.=. 3 V) is generated.
Reference voltage input pin on bottom side
Reference voltage output pin
By connecting to VRB, 0.3 × AVDD (.=. 1 V) is generated.
The values in parentheses are standard.
3
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