P4C1026-35CC Просмотр технического описания (PDF) - Semiconductor Corporation
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P4C1026-35CC Datasheet PDF : 10 Pages
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P4C1026
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym. Parameter
-15
Min Max
tRC Read Cycle Time
tAA Address Access Time
tAC Chip Enable Access Time
tOH Output Hold from Address Change
tLZ Chip Enable to Output in Low Z
tHZ Chip Disable to Output in High Z
tPU Chip Enable to Power Up Time
tPD Chip Disable to Power Down Time
15
15
15
2
2
8
0
15
-20
Min Max
20
20
20
2
3
9
0
20
-25
Min Max
25
25
25
2
3
10
0
25
-35
Unit
Min Max
35
ns
35 ns
35 ns
2
ns
3
ns
11 ns
0
ns
35 ns
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM127 REV E
Page 4 of 10
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