P4C1024L-70SI Просмотр технического описания (PDF) - Semiconductor Corporation

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P4C1024L-70SI

LOW POWER 128K x 8 CMOS STATIC RAM

Semiconductor Corporation 

P4C1024L

DATA RETENTION

Symbol

Parameter

Test Conditions

Min

VDR

VCC for Data Retention

CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V,

VIN ≥ VCC -0.2V or VIN ≤ 0.2V

2.0

I (1)

CCDR

Data Retention Current

VDR = 2.0V

VDR = 3.0V

tCDR

Chip Deselect to Data

Retention Time

See Retention Waveform

0

tR

Operating Recovery Time

5

1. CE1 ≥ VDR -0.2V, CE2 ≥ VDR -0.2V or CE2 ≤ 0.2V; or CE1 ≤ 0.2V, CE2 - 0.2V; VIN ≥ VDR -0.2V or VIN ≤ 0.2V

Max Unit

5.5

V

30 µA

50 µA

ns

ms

LOW VCC DATA RETENTION WAVEFORM 1 (CE1 CONTROLLED)

LOW VCC DATA RETENTION WAVEFORM 2 (CE2 CONTROLLED)

DATA RETENTION MODE

VCC

4.5V

tCDR

CE2

VIL 2.2V

VDR

CE2 ≤ -0.2V

4.5V

tR

VIL

Document # SRAM125 REV C

Page 7 of 10

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