P4C1024SSPT Просмотр технического описания (PDF) - Semiconductor Corporation

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P4C1024SSPT

HIGH SPEED 128K x 8 DUAL CHIP ENABLE CMOS STATIC RAM

Semiconductor Corporation 

TIMINIG WAVERFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)

P4C1024

TIMING WAVEFORM OF READ CYCLE NO. 3 (CE1, CE2 CONTROLLED)(5,7,10)

Notes:

9. READ Cycle Time is measured from the last valid address to the first

transitioning address.

10. Transitions caused by a chip enable control have similar delays

irrespective of whether CE1 or CE2 causes them.

Document # SRAM124 REV A

Page 5 of 14

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