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OZ6833

ACPI CardBus Controller

Unspecified 

Pin Name

Description

SERR#

PAR

PCI_CLK

RST#

RI_OUT

CLKRUN#

PME#

SKTB_ACTV

INTA#

System Error: This output is driven

active LOW to indicate an address parity

error.

Parity: This pin generates PCI parity and

ensures even parity across AD[31:0] and

C/BE[3:0]#. During the address phase,

PAR is valid after one clock. With data

phases, PAR is stable one clock after a

write or read transaction.

PCI Clock: This input provides timing for

all transactions on the PCI bus to and from

the OZ6833. All PCI bus signals, except

RST#, are sampled and driven on the

rising edge of PCI_CLK. This input can be

operated at frequencies from 0 to 33MHz.

Device Reset: This input is used to

initialize all registers and internal logic to

their reset states and place most OZ6833

pins in a HIGH-impedance state.

Ring Indicate Out: This pin is Ring

Indicate when the following occurs while

O2 Mode Control B Register (index 2Eh)

bit 7 is set to 1:

1) Power Control (Index+02h) bit 7 set

to 1

2) Interrupt and General Control

(Index+03h) bit 7 set to 1

3) PCI O2Micro Control 2 (Offset: D4h)

bit X = 0

PCI Clock Run Request: This signal is

used by the central resource to request

permission to stop the PCI clock or to slow

it down, and the OZ6833 responds

accordingly. To enable the CLKRUN#

signal, you need to enable ExCA register

3B bit[3:2].

Power Management Event: A power

management event is the process by

which the OZ6833 can request a change

of its power consumption state. Usually, a

PME occurs during a request to change

from a power saving state to the fully

operational state.

Socket B Activity: This signal indicates

that there is any activity on the socket B

read/write access. Refer to PCI

Configuration Register 90h.

PCI Bus Interrupt A: This output

indicates a programmable interrupt

request generated from any of a number

of card actions. Although there is no

specific mapping requirement for

connecting interrupt lines from the

OZ6833 to the system, a common use is

to connect this pin to the system PCI bus

INTA# signal.

Pin Number

TQFP

BGA

34

L2

35

L3

1

A1

207

C3

72

P8

208

B2

163

D13

193

A7

203

A3

OZ6833

Input

-

Type

TO

Power

Rail

4

Drive

PCI Spec

TTL

I/O

4

PCI Spec

TTL

I

4

-

TTL

I

1

-

-

TO

1

4mA

TTL

I/O

4

PCI Spec

-

TO

5

4mA

-

TO

1

4mA

-

TO

4

PCI Spec

OZ6833-DS-1.55

Page 6

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