GLT6200L08LL-70FG Просмотр технического описания (PDF) - G-Link Technology
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GLT6200L08LL-70FG Datasheet PDF : 12 Pages
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G-LINK
GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Nov 2000(Rev. 1.0)
Timing Waveform of Read Cycle 1 (3,6,7,9) (Address Controlled)
Address
tRC
tAA
tOH
DOUT
Data Valid
Timing Waveform of Read Cycle 2 (5,6,8,9) ( CE1 Controlled)
CE1
tRC
OE
tOE
tACE
tOLZ
tOHZ
tCHZ
DOUT
tCLZ
Data Valid
Supply Current
tPU
50%
tPD
ICC
50%
ISB
Write Cycle (3,11)( Vcc=2.7V to 3.3V, TA =-25°C to + 85°C)
Parameter
Write Cycle Time
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
Write Pulse Width
Write Recovering Time
Data Valid to Write End
Data Hold Time
Write Enable to Output in High-Z
Output Active from Write End
Symbol
tWC
tCW
tAW
tAS
tWP
tWR
tDW
tDH
tWZ
tOW
55
Min
Max
55
40
40
0
40
0
25
0
25
5
70
Min
Max
70
60
60
0
50
0
30
0
30
5
85
Min
Max
85
70
70
0
60
0
35
0
35
5
Unit Note
ns
ns
ns
ns
ns
ns
ns
ns
ns 4,5
ns 4,5
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
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G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
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