BS616LV2015 Просмотр технического описания (PDF) - Brilliance Semiconductor
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BS616LV2015 Datasheet PDF : 11 Pages
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BSI Very Low Power/Voltage CMOS SRAM
128K X 16 bit
BS616LV2015
FEATURES
• Very low operation voltage : 4.5 ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 40mA (Max.) operating current
I -grade: 45mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc = 5.0V
-55
55ns (Max.) at Vcc = 5.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The BS616LV2015 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.6uA and maximum access time of 70/55ns in 5V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE), active LOW output enable(OE) and three-state output
drivers.
The BS616LV2015 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2015 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package, JEDEC standard 44-pin TSOP Type II package
and 48-pin BGA package.
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
BS616LV2015DC
BS616LV2015EC
BS616LV2015TC
BS616LV2015AC
BS616LV2015DI
BS616LV2015EI
BS616LV2015TI
BS616LV2015AI
+0 O C to +70 O C
-40 O C to +85 O C
PIN CONFIGURATIONS
4.5V ~ 5.5V
4.5V ~ 5.5V
SPEED
(ns)
Vcc=5.0V
70 / 55
POWER DISSIPATION
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
Vcc=5.0V
Vcc=5.0V
6uA
40mA
70 / 55
10uA
BLOCK DIAGRAM
45mA
PKG TYPE
DICE
TSOP2-44
TSOP1-48
BGA-48-0608
DICE
TSOP2-44
TSOP1-48
BGA-48-0608
A4
1
A3
2
A2
3
A1
4
A0
5
CE
6
DQ0
7
DQ1
8
DQ2
9
DQ3
10
VCC
11
GND
12
DQ4
13
DQ5
14
DQ6
15
DQ7
16
WE
17
A16
18
A15
19
A14
20
A13
21
A12
22
44
43
42
41
40
39
38
37
BS616LV2015EC
36
35
BS616LV2015EI 34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
6
A
LB
OE
A0
A1
A2
N.C.
B
D8
UB
A3
A4
CE
D0
A8
A13
A15
Address
A16
20
1024
A14
Input
Row
A12
A7
Buffer
Decoder
A6
A5
A4
16
DQ0
.
.
Data
Input
16
Buffer
.
.
.
.
16
.
.
Data
Output
16
DQ15
Buffer
Memory Array
1024 x 2048
2048
Column I/O
Write Driver
Sense Amp
128
Column Decoder
C
D9
D10
A5
A6
D1
D2
D
VSS D11 N.C.
A7
D3
VCC
E
VCC D12 N.C. A16
D4
VSS
F
D14 D13 A14 A15
D5
D6
G
D15 N.C. A12
A13
WE
D7
CE
WE
OE
UB
LB
Vcc
Gnd
Control
14
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
H
N.C.
A8
A9
A10
A11 N.C.
48-ball BGA top view
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV2015
1
Revision 2.5
April 2002
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