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OP220AZ
(Rev.:RevA)

Dual Micropower Operational Amplifier

Analog Devices 

OP220–SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V

Differential Input Voltage . . . . . . . . . . 30 V or Supply Voltage

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage

Output Short-Circuit Duration

Indefinite

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Junction Temperature (Ti) . . . . . . . . . . . . . –65∞C to +150∞C

Operating Temperature Range

OP220A/OP220C . . . . . . . . . . . . . . . . . . –55∞C to +125∞C

OP220E/OP220F . . . . . . . . . . . . . . . . . . . . –25∞C to +85∞C

OP220G . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C

Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300∞C

NOTES

*Absolute Maximum Ratings apply to packaged parts, unless otherwise noted.

DIE CHARACTERISTICS

DIE SIZE 0.097 INCH ؋ 0.063 INCH, 6111 SQ. MILS

(2.464 mm ؋ 1.600 mm, 3.94 SQ. mm)

NOTE : ALL V+ PADS ARE INTERNALL CONNECTED

1. INVERTING INPUT (A)

2. NONINVERTING INPUT (A)

3. BALANCE (A)

4. V–

5. BALANCE (B)

6. NONINVERTING INPUT (B)

7. INVERTING INPUT (B)

8. BALANCE (B)

9. V+

10. OUT (B)

11. V+

12. OUT (A)

13. V+

14. BALANCE (A)

Package Type

␪JA*

8-Lead Hermetic DIP (Q)

148

8-Lead Plastic DIP (N)

103

8-Lead SOL (RN)

158

TO-99 (H)

150

␪JC

Unit

16

∞C/W

43

∞C/W

43

∞C/W

18

∞C/W

*␪JA is specified for worst-case mounting conditions, i.e., ␪JA is specified for device

in socket for CERDIP and PDIP packages; ␪JA is specified for device soldered to

printed circuit board for SO packages.

ORDERING GUIDE

TA = 25∞C

Package Options

VOS MAX

(mV)

CERDIP Plastic

TO-99

150

OP220AZ*

150

OP220EZ*

300

OP220FZ*

750

OP220CJ* MIL

750

OP220GZ* OP220GP*

750

OP220GS

Operating

Temperature

Range

MIL

IND

IND

XIND

XIND

For military processed devices, please refer to the Mil Standard

Data Sheet

OP220AJ/883*.

*Not for new design. Obsolete April 2002.

WAFER TEST LIMITS (@ VS = ؎2.5 V, to ؎15 V, TA = 25؇C, unless otherwise noted.)

Parameter

Symbol

Conditions

OP220N

Limit

Unit

Input Offset Voltage

Input Offset Voltage Match

Input Offset Current

Input Bias Current

Input Voltage Range

Common-Mode

Rejection Ratio

Power Supply

Rejection Ratio

VOS

⌬VOS

IOS

IB

IVR

CMRR

PSRR

VCM = 0

VCM = 0

VS = ± 15 V

V– = 0 V, V+ = 5 V, 0 V £ VCM £ 3.5 V

–15 V £ VCM £ 13.5 V, VS = ± 15 V

VS = ± 2.5 V to ± 15 V

V– = 0 V, V+ = 5 V to 30 V

200

300

2

25

–15/13.5

88

93

12.5

22.5

mV Max

mV Max

nA Max

nA Max

V Min

dB Min

mV/V Max

Large-Signal

Voltage Gain

AVO

RL = 25 kW, VS = ± 15 V

VO = ± 10 V

1000

V/mV Min

Output Voltage Swing

VO

V+ = 5 V, V– = 0 V, RL = 10 kW

VS = ± 15 V, RL = 25 kW

0.7/4

± 14

V Min

Supply Current

ISY

(Both Amplifiers)

VS = ± 2.5 V, No Load

VS = ± 15 V, No Load

125

mA Max

190

NOTE

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packing is not guaranteed

for standard product dice. Consult factory to negotiate specifications based on die lot qualification through sample lot assembly and testing.

–4–

REV. A

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