SPT7814(1991) Просмотр технического описания (PDF) - Signal Processing Technologies

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SPT7814
(Rev.:1991)

AN7810/14 EVALUATION BOARD

Signal Processing Technologies 

U8, U9 and U10 are non-inverted (D0-D10) ECL-to-TTL data

translators. J3-J6 are the optional jumpers to obtain the

desired phase of the TTL/CCLK. When J4 and J5 are

installed the TTL/CCLK is in phase with ECL/CCLK. This

option is factory installed. If a 180° out of phase is desired

between ECL/CCLK and TTL/CCLK then replace J4 and J5

by J3 and J6. Table VI shows the pin-out assignment of the

TTL data output from the ribbon connector P2.

Figure 4 -

Timing Diagram

U1* N-1

N

INPUT (-)

N+1

N+2

N+3

N+4

CLK IN * *

NCLK

t pd1

tpwH t pwL

CLK

DATA

VALID

(ECL)

t pd2

(N-2)

(N-1)

(N)

ts

(N+1)

(N+2)

CCLK 50%

(ECL)

P1

DATA

VALID

(ECL)

(N-3)

P2

DATA

VALID

(TTL)

(N-3)

t pd3

(N-2)

(N-1)

t pd4

(N-2)

(N-1)

(N)

(N)

(N+1)

(N+2)

(N+1)

* = U1, input (-) voltage level adjustable with R20 for the desired clock positive pulse width (tpwH)

* * = CLK IN could be either sinusoidal or square wave

Table VII - Timing Specification

Function

tpd1

tdp2

tpd3

tpd4

ts

tpwH

tpwL

U1, VOS

Description

Min

CLK IN to CLK & CLK Prop. Delay

-

CLK to Data Valid Prop. Delay

-

CCLK to P1-Output Data Valid Prop. Delay

0.9

CCLK to P2-Output Data Valid Prop. Delay

-

CCLK Set-Up Time

8

CLK Pulse Width-High

12

CLK Pulse Width-Low

-

HCMP96870 offset voltage

-4

Typ

Max

Unit

2

2.3

nsec

4

-

nsec

-

2.4

nsec

6

9

nsec

-

-

nsec

-

300

nsec

-

-

nsec

-

+4

mV

SPT

AN7810/14

5

12/11/91

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