NJU6679CL Просмотр технического описания (PDF) - Japan Radio Corporation

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NJU6679CL

128-common x 132-segment BIT MAP LCD DRIVER

Japan Radio Corporation  

BLOCK DIAGRAM

VSS

VDD

5

V1 to V5

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

Voltage

Generator

VR

T1,T2

C0

C63

S0

S131

C127

C64

COM

Driver

SEG

Driver

COM

Driver

Shift

Register

Shift

Register

Display Data Latch

Display Data RAM

192 x 132

NJU6679

COM SEG

Timing

Generator

Culumn Address Decoder

Culumn Address Counter

Culumn Address Register

Mu l t i pl exe r

Display

Timing

Generator

OSC.

OSC1

OSC2

Instruction Decoder

Status

Internal Bus

BF

Bus Holder

Reset

RES

MPU Interface

RD SEL68

D0 to D7 (SI,SCL)

CS

A0

WR

P/S

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