NB2308AI1DR2G Просмотр технического описания (PDF) - ON Semiconductor

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NB2308AI1DR2G

3.3 V Zero Delay Clock Buffer

ON Semiconductor 

NB2308A

REF

Extra Divider (−5H)

B2

PLL

B2

Extra Divider (−3, −4)

MUX

S2

SELECT INPUT

DECODING

S1

B2

Extra Divider (−2, −3)

FBK

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

Figure 1. Block Diagram

(see Figures 11, 12, 13, 14 and 15 for device specific Block Diagrams)

CLKB4

Table 1. CONFIGURATIONS (x = C for Commercial; I for Industrial)

Device

Feedback From

Bank A Frequency

Bank B Frequency

NB2308Ax1

Bank A or Bank B

Reference

Reference

NB2308Ax1H

Bank A or Bank B

Reference

Reference

NB2308Ax2

Bank A

Reference

Reference B2

NB2308Ax2

Bank B

2 X Reference

Reference

NB2308Ax3

Bank A

2 X Reference

Reference or Reference (Note 1)

NB2308Ax3

Bank B

4 X Reference

2 X Reference

NB2308Ax4

Bank A or Bank B

2 X Reference

2 X Reference

NB2308Ax5H

Bank A or Bank B

Reference B2

Reference B2

1. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the NB2308Ax2.

Table 2. SELECT INPUT DECODING

S2

S1

Clock A1 − A4

Clock B1 − B4

0

0

Three−state

Three−state

0

1

Driven

Three−state

1

0

Driven (Note 2)

Driven

1

1

Driven

Driven

2. Outputs inverted on 2308−2 and 2308−3 in bypass mode, S2 = 1 and S1 = 0.

Output Source

PLL

PLL

Reference

PLL

PLL ShutDown

Y

N

Y

N

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