+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
Timing Diagrams
5V
D
0
V0
B—A
-V0
A
B
1.5V
tPLH
50%
90%
10%
tr
f = 1MHz: tr ≤10ns: tf ≤ 10ns
VDIFF = V(A) - V(B)
1/2 V0
V0
tSKEW
Figure 6. V.11, V.35 Driver Propagation Delays
1.5V
tPHL
90%
50% 10%
tf
tSKEW
V0
B—A
-V0
V0H
R
V0L
0
tPLH
1.5V
Figure 7. V.11, V.35 Receiver Propagation Delays
f = 1MHz: tr ≤10ns: tf ≤ 10ns
3V
D
1.5V
0
tPHL
V0
3V
A
0
-3V
-V0
tr
Figure 8. V.28 Driver Propagation Delays
INPUT
0
tPHL
OUTPUT
1.5V
1.5V
tPLH
3V
0
-3V
tr
VIH
A
1.3V
VIL
tPHL
V0H
R
V0L
0.8V
Figure 9. V.28 Receiver Propagation Delays
1.7V
tPLH
2.4V
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