MX98741 Просмотр технического описания (PDF) - Macronix International

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MX98741

XRC 100 BASE-TX/FX REPEATER CONTROLLER

Macronix International 

5.2 INTERNAL REGISTERS

There are two ways to access the XRC internal regis-

ters.

All the registers can be accessed through MII's MDC

and MDIO. Although XRC connects to multiple 100-TX

PHY's, they are all identical. Each XRC has only one

PHY address as defined by ACTP[4:0] pins. If multiple

XRC's are on the same MDIO bus, each of them should

have different PHY address. Other non-XRC PHY de-

vices (e.g. T4) are also allowed to be managed with the

same management interface as long as PHY address

of each device is distinct.

Another way to access registers is through register ac-

cess pins. Register 17 (Scrambler Enable and Port

Enable), Register 18 (Link Status, Partition Status),

Register 19 (Elastic Buffer Status and Jabber Status),

Register 20 (Isolation Status), Register 21 (Isolation

Disable and Partition Disable) can also be read through

PTSCEN, PARTLNK, JBFLO, ISO and PIDIS, respec-

tively. The exception are register 0 (Command Regis-

ter), register 1 (Status Register), and register 16 (Port

Reset Register) which can only be accessed through

MDC and MDIO. The register access pins facilitate a

simple read/write protocol suitable for hardware-only

configuration and status display design.

MX98741

P/N:PM0342

REV. 1.4, NOV. 07, 1996

10

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