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MX29F040

4M-BIT [512KX8] CMOS EQUAL SECTOR FLASH MEMORY

Macronix International 

MX29F040

AUTOMATIC PROGRAMMING

The MX29F040 is byte programmable using the Auto-

matic Programming algorithm. The Automatic Program-

ming algorithm makes the external system do not need

to have time out sequence nor to verify the data pro-

grammed. The typical chip programming time at room

temperature of the MX29F040 is less than 4 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typical erasure at room temperature is accomplished in

less than 4 second. The Automatic Erase algorithm au-

tomatically programs the entire array prior to electrical

erase. The timing and verification of electrical erase are

controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29F040 is sector(s) erasable using MXIC's

Auto Sector Erase algorithm. Sector erase modes

allow sectors of the array to be erased in one erase

cycle. The Automatic Sector Erase algorithm

automatically programs the specified sector(s) prior to

electrical erase. The timing and verification of

electrical erase are controlled internally within the

device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm require the user

to only write program set-up commands (including 2 un-

lock write cycle and A0H) and a program command (pro-

gram data and address). The device automatically times

the programming pulse width, provides the program veri-

fication, and counts the number of sequences. A status

bit similar to DATA polling and a status bit toggling be-

tween consecutive read cycles, provide feedback to the

user as to the status of the programming operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stand-

ard microprocessor write timings. The device will auto-

matically pre-program and verify the entire array. Then

the device automatically times the erase pulse width,

provides the erase verification, and counts the number

of sequences. A status bit toggling between consecu-

tive read cycles provides feedback to the user as to the

status of the programming operation.

Register contents serve as inputs to an internal state-

machine which controls the erase and programming cir-

cuitry. During write cycles, the command register inter-

nally latches address and data needed for the program-

ming and erase operations. During a system write cycle,

addresses are latched on the falling edge of WE or CE,

whichever happens later, and data are latched on the

rising edge of WE or CE, whichever happens first.

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, relia-

bility, and cost effectiveness. The MX29F040 electrically

erases all bits simultaneously using Fowler-Nordheim

tunneling. The bytes are programmed by using the

EPROM programming mechanism of hot electron injec-

tion.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Erase

Suspend command. After Erase Suspend is completed,

the device stays in read mode. After the state machine

has completed its task, it will allow the command regis-

ter to respond to its full command set.

P/N:PM0538

REV. 2.3, DEC. 10, 2004

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