UD61464DC08 Просмотр технического описания (PDF) - Zentrum Mikroelektronik Dresden AG
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UD61464DC08 Datasheet PDF : 14 Pages
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UD61466
Dynamic Characteristics
3)
F SCM Read
Column Address Hold Time ref. to RAS Rise 10)
Output Data Hold Time from Column
Address
F SCM Write
Symbol
Alt.
IEC
Min.
Max.
Unit
DC07 DC08 DC07 DC08
tAH
th(RASH-CA)
5
5
ns
tAOH
tv(CA)
5
5
ns
Write Command Inactive Time
F SCM Read-Write
tWI
tw(WH)
10
10
ns
Static Column Mode Read-Write Cycle Time
tSRWC
tc(A)RW
100 110
ns
Access Time from Last Write
tALW
ta(WL)
65
75
ns
Output Data Enable Time from WRITE
tOW
ta(WH)
35
40
ns
F HIDDEN REFRESH
CAS Hold Time (CAS before RAS Cycle)
tCHR
tRASL-CASH
15
15
ns
Remark: see below
Remarks:
1) The Input Low Voltage must not
drop below -0.3 V for more than
40 ns.
1a) The total sum of the absolute
values of output currents must
not exceed 100 mA in case of
static application.
2) The current is inversely propor-
tional to the cycle time; the
max. current is measured in the
shortest cycle time.
3) For test conditions see test con-
figuration for functional test
and clock timing.
4) VIHmin and VILmax are reference
levels for time measurement of
the input signals; transition
times are measured between
VIH and VIL.
5) tv(CAS) and tv(G) define the time
at which the data output goes to
High-Z; this time is not related
to any level.
December 12, 1997
6) tRASL-CASLmax and tv(G) are given
as reference points only; they
do not represent restrictive con-
ditions.
7) The values of tcWmin, tcRmin and
tcRWmin are used for indication of
the particular cycle time in
which full function is guaran-
teed in the temperature range
from 0 to 70 °C. Values below
the one shown above may
cause permanent damage to
the component.
8) Measured with a load equiva-
lent to 2 TTL loads, 100 pF
9) In Read cycle either th(RAS-R) or
th(CAS-R) must be kept.
10) th(RASH-CA) is only required if the
valid data are to be held beyond
the rising edge of RAS.
11) tsu(W-CAS), tRAS-W, tCAS-W and
t(CA-W)RW do not represent
restrictive parameters:
- if tsu(W-CAS) ≥ tsu(W-CAS)min and
th(CASH-W) ≥ th(CASH-W)min, the
7
cycle is a Write cycle (CAS-con-
trolled), and the data output
remains in High-Z throughout
the whole cycle,
- if tCAS-W > tCAS-Wmin, tRAS-W
> tRAS-Wmin and t(CA-W)RW > t(CA-
W)RWmin, the cycle is a Read-
Write cycle, and the content of
the cell is available at the data
output,
- if none of these conditions is
satisfied, the condition of the
data output (at access time) is
indeterminate, since a Write
cycle (W-controlled) is carried
out.
12) These parameters refer to CAS
during Write (CAS-controlled),
and to W (W-controlled) or to W
during Read-Write.
13) Timing of CAS in SCM is neces-
sary only if the data output is to
go to High-Z between the read-
out of two successiv column
addresses.
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