UD61466 Просмотр технического описания (PDF) - Zentrum Mikroelektronik Dresden AG
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UD61466 Datasheet PDF : 14 Pages
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UD61466
Block Diagram
G
CAS
W
Output Control
Write-Read-Control
RAS
Clock Generator
Data Input and
Output Amplifier
4 Write-Read-Amplifiers
DQ0
DQ1
DQ2
DQ3
A0
A1
A2
A3
A4
A5
A6
A7
Operation
M
U
X
A0X to A7X
A0Y to A7Y
Function
RAS
CAS
Stand-by
Read
Write
H
X
L
L
L
L
Read-Write
L
L
SCM
Read
SCM
Write
1st
cycle
L
L
2nd
cycle
L
L
1st
cycle
L
L
2nd
cycle
L
L
SCM
1st
cycle
L
L
Read-Write
2nd
cycle
L
L
RAS only Refresh
L
H
HIDDEN
Refresh*)
Read L → H → L
L
Write L → H → L
L
*) Transfer of Refresh Address required
Row
Decoder
Row
Decoder
W
X
H
L
H→L
H
H
L
H→L
H→L
H→L
X
H
L
VCC VSS
Address
G
R
C
X
X
X
Row
Column
L
Row
Column
X
Row
Column L → H
Row
Column
L
Column
L
Row
Column
X
Data
High-Z
Output
Data
Input Data
Output
Data/Input
Data
Output
Data
Output
Data
Input Data
Row
Row
Row
Row
Column
Column
Column
Column
Column
X
L→H
L→H
X
L
X
Input Data
Output
Data/Input
Data
Output
Data/Input
Data
High-Z
Output
Data
Input Data
2
December 12, 1997
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