MT9046 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

Номер в каталоге

Компоненты Описание

Список матч

MT9046

T1/E1 System Synchronizer with Holdover

Zarlink Semiconductor Inc 

MT9046

Data Sheet

Pin Description (continued)

Pin #

18

19

20

21

22

24

25

26

27

29

30

32

33,34

36

37

38

39

40

41

42

43

44

Name

Description

LOCK Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to

the input reference.

C2o Clock 2.048 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s.

C4o Clock 4.096 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s

and 4.096 Mb/s.

C19o Clock 19.44 MHz (CMOS Output). This output is used in OC3/STS3 applications.

FLOCK Fast Lock Mode (Input). Set high to allow the PLL to quickly lock to the input reference

(less than 500 ms locking time).

IC Internal Connection. Tie low for normal operation.

C8o Clock 8.192 MHz (CMOS Output). This output is used for ST-BUS operation at 8.192 Mb/s.

C16o Clock 16.384 MHz (CMOS Output). This output is used for ST-BUS operation with a

16.384 MHz clock.

C6o Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.

HOLD Holdover (CMOS Output). This output goes to a logic high whenever the PLL goes into

OVER holdover mode.

PCCi

Phase Continuity Control Input (Input). The signal at this pin affects the state changes

between Primary Holdover Mode and Primary Normal Mode, and Primary Holdover Mode and

Secondary Normal Mode. The logic level at this input is gated in by the rising edge of F8o.

See Table 4.

NC No connection. Leave open circuit

IC Internal Connection. Tie low for normal operation.

MS2

Mode/Control Select 2 (Input). This input determines the state (Normal, Holdover or

Freerun) of operation. The logic level at this input is gated in by the rising edge of F8o. See

Table 3.

MS1 Mode/Control Select 1 (Input). The logic level at this input is gated in by the rising edge of

F8o. See pin description for MS2. This pin is internally pulled down to VSS.

RSEL

Reference Source Select (Input). A logic low selects the PRI (primary) reference source as

the input reference signal and a logic high selects the SEC (secondary) input. The logic level

at this input is gated in by the rising edge of F8o. See Table 2. This pin is internally pulled

down to VSS.

IC Internal Connection. Tie low for normal operation.

FS2 Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four

possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI

and SEC inputs. See Table 1.

FS1 Frequency Select 1 (Input). See pin description for FS2.

IC Internal Connection. Tie low for normal operation.

NC No Connection. Leave open Circuit

TDO Test Serial Data Out (CMOS Output). JTAG serial data is output on this pin on the falling

edge of TCK. This pin is held in high impedance state when JTAG scan is not enable.

4

Zarlink Semiconductor Inc.

Share Link: