![](/html/Mitel/527685/page6.png)
MT8806 ISO-CMOS
tCSS
50%
CS
tCSH
50%
tRPW
RESET
tSPW
50%
STROBE
ADDRESS
tAS
50%
50% 50%
50%
50%
tAH
DATA
50%
50%
tDS
tDH
ON
SWITCH*
OFF
tD
tS
tR
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
50%
tR
AX0
0
0
0
0
0
0
0
0
1
↓
1
0
↓
0
1
↓
1
AX1
0
0
0
0
0
0
0
0
0
↓
0
1
↓
1
1
↓
1
AY0
AY1
AY2
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
↓
↓
↓
1
1
1
0
0
0
↓
↓
↓
1
1
1
0
0
0
↓
↓
↓
1
1
1
Table 1. Address Decode Truth Table
Connection
X0-Y0
X0-Y1
X0-Y2
X0-Y3
X0-Y4
X0-Y5
X0-Y6
X0-Y7
X1-Y0
↓↓
X1-Y7
X2-Y0
↓↓
X2-Y7
X3-Y0
↓↓
X3-Y7
3-14