HB52E649E12 Просмотр технического описания (PDF) - Elpida Memory, Inc

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HB52E649E12

512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC100 SDRAM

Elpida Memory, Inc 

HB52E649E12-A6B/B6B

DC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)

HB52E649E12

-A6B

-B6B

Parameter

Symbol Min Max Min Max Unit Test conditions Notes

Operating current

(CE latency = 3)

I CC1

(CE latency = 4)

I CC1

Standby current in power ICC2P

down

Burst length = 1 1, 2, 3

—

2220 —

—

mA

tRC = min

—

2220 —

2220 mA

—

564 —

564 mA

CKE = VIL, tCK = 12 6

ns

Standby current in power ICC2PS

—

546 —

546 mA

CKE = VIL, tCK = ∞ 7

down (input signal stable)

Standby current in non ICC2N

—

870 —

870 mA

CKE, S = VIH,

4

power down

tCK = 12 ns

Active standby current in ICC3P

power down

—

582 —

582 mA

CKE = VIL, tCK = 12 1, 2, 6

ns

Active standby current in ICC3N

non power down

Burst operating current

(CE latency = 3)

I CC4

(CE latency = 4)

I CC4

Refresh current

I CC5

Self refresh current

I CC6

Input leakage current

I LI

Output leakage current ILO

—

1050 —

1050 mA

—

2220 —

—

mA

—

2220 —

2220 mA

—

4470 —

4470 mA

—

564 —

564 mA

–10 10

–10 10

µA

–10 10

–10 10

µA

CKE, S = VIH,

tCK = 12 ns

tCK = min, BL = 4

1, 2, 4

1, 2, 5

VIH ≥ VCC – 0.2 V

8

VIL ≤ 0.2 V

0 ≤ Vin ≤ VCC

0 ≤ Vout ≤ VCC

DQ = disable

Output high voltage

VOH

2.4 —

2.4 —

V

IOH = –4 mA

Output low voltage

VOL

—

0.4 —

0.4 V

IOL = 4 mA

Notes: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the

output open condition.

2. One bank operation.

3. Input signals are changed once per one clock.

4. Input signals are changed once per two clocks.

5. Input signals are changed once per four clocks.

6. After power down mode, CK operating current.

7. After power down mode, no CK operating current.

8. After self refresh mode set, self refresh current.

Data Sheet E0020H20

10

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