MSM5267B-15 Просмотр технического описания (PDF) - Oki Electric Industry

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MSM5267B-15

33-BIT VFD SEGMENT DRIVER

Oki Electric Industry 

¡ Semiconductor

MSM5267B-15

FUNCTIONAL DESCRIPTION

• Data Input

The data pattern (33 bits) supplied to the device through this input control the output driver

state (On or Off).

1. A high level turns the output driver on.

2. A low level turns the output driver off.

• Clock Input

A Positive transition of the clock loads and shifts the data. This input also has a Schmitt

trigger which provides 0.3 volts of hysteresis.

• Blanking Input

A low-level voltage at this pin turns the output drivers off; an internal pull up is provided

on this pin.

• Load Enable

A high-level at this input transfers the data from the shift register to the data latch, and sets

the shift register to zero.

First data bit read-in stored in a shift register #1, the last data bit read-in is stored in a shift

register #33. When the shift registers are full, a high voltage level applied to the load enable

input will transfer the data from the shift register to the data latch, and then to the output.

The device has 34 shift registers and 33 data latches as shown in the functional block

diagram.

There are two modes of operation:

VDD

FROM

MICROPROCESSOR

DATA

CLOCK

BLANK

LOAD ENABLE

DATA OUT

1

2

3

40

38

37

39

33 OUTPUTS

• Self-Load Mode

In this mode Data Out (pin37) is connected to Load Enable (pin38), and the data word is

constructed with 33 bits (including the one self-load bit set to logic 1). At the 34th clock pulse,

the data is transferred from the shift register to the data latch and the output drivers. Before

the next clock pulse, the registers are zeroed.

• Non-Self-Load Mode

In this mode, the Data Out and the Load Enable pins are not connected, and the Load Enable

input is controlled by an external source. (There are two types of operation in this mode.)

1. The data word consists of 34 bits (including one self-load bit). To transfer data from the shift

registers to the data latch, a high-level voltage is applied to the Load Enable pin before the

rise of the clock pulse following the 34th clock pulse.

2. The data word consists of 33 bits without the self-load bit. To transfer the data, a high voltage

level is applied to the Load Enable pin before the rise of the 34th clock pulse.

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